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| altera corporation section i?1 preliminary section i. hardcopy stratix device family data sheet this section provides designers with the data sheet specifications for hardcopy ? stratix structured asics. the chapters contain feature definitions of the internal architecture, jtag boundary-scan testing information, dc operating conditions, ac timing parameters, and a reference to power consumption for hardcopy stratix structured asics. this section contains the following: chapter 1, introduction to hardcopy stratix devices chapter 2, description, architecture, and features chapter 3, boundary-scan support chapter 4, operating conditions chapter 5, quartus ii support for hardcopy stratix devices chapter 6, design guidelines for hardcopy stratix performance improvement revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the complete handbook. www.datasheet.in
section i?2 altera corporation preliminary revision history hardcopy series handbook, volume 1 www.datasheet.in altera corporation 1?1 september 2008 preliminary 1. introduction to hardcopy stratix devices introduction hardcopy ? stratix ? structured asics, altera?s second-generation hardcopy structured asics, are low-cost, high-performance devices with the same architecture as the high-density stratix fpgas. the combination of stratix fpgas for prototyping and design verification, hardcopy stratix devices for high-volume production, and the quartus ? ii design software beginning with version 3.0, provide a complete and powerful alternative to asic design and development. hardcopy stratix devices are architecturally equivalent and have the same features as the corresponding stratix fpga. they offer pin-to-pin compatibility using the same package as the corresponding stratix fpga prototype. designers can prototype their design to verify functionality with stratix fpgas before seamlessly migrating the proven design to a hardcopy stratix structured asic. the quartus ii software provides a complete set of inexpensive and easy-to-use tools for designing hardcopy stratix devices. using the successful and proven methodology from hardcopy apex? devices, stratix fpga designs can be seamlessly and quickly migrated to a low-cost asic alternative. designers can use the quartus ii software to design hardcopy stratix devices to obtain an average of 50% higher performance and up to 40% lower power consumption than can be achieved in the corresponding stratix fpgas. the migration process is fully automated, requires minimal customer involvement, and takes approximately eight weeks to deliver fully tested hardcopy stratix prototypes. the hardcopy stratix devices use the same base arrays across multiple designs for a given device density and are customized using the top two metal layers. the hardcopy stratix family consists of the hc1s25, hc1s30, hc1s40, HC1S60, and hc1s80 devices. table 1?1 provides the details of the hardcopy stratix devices. h51001-2.4 www.datasheet.in 1?2 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 features hardcopy stratix devices are manufactured on the same 1.5-v, 0.13 m all-layer-copper metal fabrication process (up to eight layers of metal) as the stratix fpgas. preserves the functionality of a configured stratix device pin-compatible with the stratix counterparts on average, 50% faster than their stratix equivalents on average, 40% less power consumption than their stratix equivalents 25,660 to 79,040 les up to 5,658,408 ram bits available trimatrix memory architecture consisting of three ram block sizes to implement true dual-port memory and first-in-first-out (fifo) buffers embedded high-speed dsp blocks provide dedicated implementation of multipliers, multiply-accumulate functions, and finite impulse response (fir) filters up to 12 plls (four enhanced plls and eight fast plls) per device which provide identical features as the fpga counterparts, including spread spectrum, programmable bandwidth, clock switchover, real-time pll reconfiguration, advanced multiplication, and phase shifting supports numerous single-ended and differential i/o standards supports high-speed networking and communications bus standards including rapidio?, utopia iv, csix, hypertransport technology, 10g ethernet xsbi, spi-4 phase 2 (pos-phy level 4), and sfi-4 differential on-chip termination support for lvds table 1?1. hardcopy stratix devices and features device les (1) m512 blocks m4k blocks m-ram blocks dsp blocks (2) plls (3) hc1s25 25,660 224 138 2 10 6 hc1s30 32,470 295 171 2 (4) 12 6 hc1s40 41,250 384 183 2 (4) 14 6 HC1S60 57,120 574 292 6 18 12 hc1s80 79,040 767 364 6 (4) 22 12 notes to tab le 1 ?1 : (1) le: logic elements. (2) dsp: digital signal processing. (3) plls: phase-locked loops. (4) in hc1s30, hc1s40, and hc1s80 devices, there are fewer m-ram blocks than in the equivalent stratix fpga. all other resources are identical to the stratix counterpart. www.datasheet.in altera corporation 1?3 september 2008 preliminary features supports high-speed external memory, including zero bus turnaround (zbt) sram, quad data rate (qdr and qdrii) sram, double data rate (ddr) sdram, ddr fast-cycle ram (fcram), and single data rate (sdr) sdram support for multiple intellectual property (ip) megafunctions from altera ? megacore ? functions, and altera megafunction partners program (ampp sm ) megafunctions available in space-saving flip-chip fineline bga ? and wire-bond packages ( tables 1?2 and 1?3 ) optional emulation of original fpga configuration sequence optional instant-on power-up 1 the actual performance and power consumption improvements over the stratix equivalents mentioned in this data sheet are design-dependent. table 1?2. hardcopy stratix device package options and i/o pin counts note (1) device 672-pin fineline bga (2) 780-pin fineline bga (3) 1,020-pin fineline bga (3) hc1s25 473 hc1s30 597 hc1s40 613 (4) HC1S60 782 hc1s80 782 notes to tab le 1 ?2 : (1) quartus ii i/o pin counts include one additional pin, pllena , which is not a general-purpose i/o pin. pllena can only be used to enable the plls. (2) this device uses a wire-bond package. (3) this device uses a flip-chip package. (4) in the stratix ep1s40f780 fpga, the i/o pins u12 and u18 are general-purpose i/o pins. in the fpga prototype, ep1s40f780_hardcopy_fpga_prototype, and in the hardcopy stratix hc1s40f780 device, u12 and u18 must be connected to ground. the ep1s40f780_hardcopy_fpga_prototype and hc1s40f780 pin-outs are identical. www.datasheet.in 1?4 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 document revision history table 1?4 shows the revision history for this chapter. table 1?3. hardcopy stratix device package sizes device 672-pin fineline bga 780-pin fineline bga 1,020-pin fineline bga pitch (mm) 1.00 1.00 1.00 area (mm 2 ) 729 841 1,089 length width (mm mm) 27 27 29 29 33 33 table 1?4. document revision history date and document version changes made summary of changes september 2008 v2.4 revised chapter number and metadata. ? june 2007 v2.3 updated introduction section. updated table 1?2 . ? december 2006 v2.2 updated revision history. ? march 2006 formerly chapter 5; no content change. ? october 2005 v2.1 minor edits ? january 2005 v2.0 minor edits ? june 2003 v1.0 initial release of chapter 5, introduction to hardcopy stratix devices , in the hardcopy device handbook . www.datasheet.in altera corporation 2?1 september 2008 2. description, architecture, and features introduction hardcopy ? stratix ? structured asics provide a comprehensive alternative to asics. the hardcopy stratix device family is fully supported by the quartus ? ii design software, and, combined with a vast intellectual property (ip) portfolio, provides a complete path from prototype to volume production. designers can now procure devices, tools, and altera ? ip for their high-volume applications. as shown in figure 2?1 , hardcopy stratix devices preserve their stratix fpga counterpart?s architecture, but the programmability for logic, memory, and interconnect is removed. hardcopy stratix devices are also manufactured in the same process technology and process voltage as stratix fpgas. removing all configuration and programmable routing resources and replacing it with direct metal interconnect results in considerable die size reduction and the ensuing cost savings. figure 2?1. hardcopy stratix device architecture m512 ram blocks for dual-port memory, shift registers, & fifo buffers dsp blocks for multiplication and full implementation of fir filters m4k ram blocks for true dual-port memory & other embedded memory functions ioes support ddr, pci, gtl+, sstl-3, sstl-2, hstl, lvds, lvpecl, pcml, hypertransport & other i/o standards ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes labs labs ioes labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs ioes labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs ioes ioes labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs dsp block m-ram block h51002-3.4 www.datasheet.in 2?2 altera corporation september 2008 hardcopy stratix and stratix fpga differences the hardcopy stratix family consists of base arrays that are common to all designs for a particular device density. design-specific customization is done within the top two metal layers. the base arrays use an area-efficient sea-of-logic-elements (sole) core and extend the flexibility of high-density stratix fpgas to a cost-effective, high-volume production solution. with a seamless migration process employed in numerous successful designs, functionality-verified stratix fpga designs can be migrated to fixed-function hardcopy stratix devices with minimal risk and guaranteed first-time success. the sram configuration cells of the original stratix devices are replaced in hardcopy stratix devices by metal connects, which define the function of each logic element (le), digital signal processing (dsp) block, phase-locked loop (pll), embedded memory, and i/o cell in the device. these resources are interconnected using metallization layers. once a hardcopy stratix device has been manufactured, the functionality of the devi ce i s fixe d and n o re-programmi ng i s pos sibl e. howeve r, as is th e cas e with stratix fpgas, the plls can be dynamically configured in hardcopy stratix devices. hardcopy stratix and stratix fpga differences to ensure hardcopy stratix device functionality and performance, designers should thoroughly test the original stratix fpga-based design for satisfactory results before committing the design for migration to a hardcopy stratix device. unlike stratix fpgas, hardcopy stratix devices are customized at the time of manufacturing and therefore do not have programmability support. since hardcopy stratix devices are customized within the top two metal layers, no configuration circuitry is required. refer to ?power-up modes in hardcopy stratix devices? on page 2?7 for more information. depending on the design, hardcopy stratix devices can provide, on average, a 50% performance improvement over equivalent stratix fpgas. the performance improvement is achieved by die size reduction, metal interconnect optimization, and customized signal buffering. hardcopy stratix devices consume, on average, 40% less power than their equivalent stratix fpgas. 1 designers can use the quartus ii software to design hardcopy stratix devices, estimate performance and power consumption, and maximize system throughput. www.datasheet.in altera corporation 2?3 september 2008 description, architecture, and features table 2?1 illustrates the differences between hardcopy stratix and stratix devices. table 2?1. hardcopy stratix and stratix device comparison (part 1 of 2) hardcopy stratix stratix customized device. all reprogrammability support is removed and no configuration is required. re-programmable with configuration is required upon power-up. average of 50% performance improvement over corresponding fpga (1) . high-performance fpga. average of 40% less power consumption compared to corresponding fpga (1) . standard fpga power consumption. contact altera for information regarding specific ip support. ip support for all devices is available. double data rate (ddr) sdram maximum operating frequency is pending characterization. ddr sdram can operate at 200 mhz for -5 speed grade devices. all routing connections are direct and all unused routing is removed. multitrack? routing stitches together routing resources to provide a path. hc1s30 and hc1s40 devices have two m-ram blocks. hc1s80 devices have six m-ram blocks. ep1s30 and ep1s40 devices have four m-ram blocks. ep1s80 devices have nine m-ram blocks. it is not possible to initialize m512 and m4k ram contents during power-up. the contents of m512 and m4k ram blocks can be preloaded during configuration with data specified in a memory initialization file ( .mif ). the contents of memory output registers are unknown after power-on reset (por). the contents of memory output registers are initialized to '0' after por. hc1s30 and hc1s40 devices have six plls. hc1s30 devices have 10 plls. hc1s40 devices have 12 plls. pll dynamic reconfiguration uses rom for information. this reconfiguration is performed in the back-end and does not affect the migration flow. pll dynamic reconfiguration uses a mif to initialize a ram resource with information. the i/o elements (ioes) are equivalent but not identical to fpga ioes due to slight design optimizations for hardcopy devices. the ioes are optimized for the fpga architecture. www.datasheet.in 2?4 altera corporation september 2008 logic elements logic elements logic is implemented in hardcopy stratix devices using the same architectural units as the stratix device family. the basic unit is the logic element (le) with logic array blocks (lab) consisting of 10 les. the implementation of les and labs is identical to the stratix device family. in the hardcopy stratix device family, all extraneous routing resources not essential to the specific design are removed for performance and die size efficiency. therefore, the multitrack interconnect for routing implementation between labs and other device resources in the stratix device family is no longer necessary in the hardcopy stratix device family. table 2?2 illustrates the differences between hardcopy stratix and stratix logic. embedded memory trimatrix? memory blocks from stratix devices, including m512, m4k, and m-ram memory blocks, are available in hardcopy stratix devices. embedded memory is seamlessly implemented in the equivalent resource. the i/o drive strength for single-ended i/o pins are slightly different and is modeled in the hardcopy stratix ibis models. the i/o drive strength for single-ended i/o pins are found in stratix ibis models. in the hc1s40 780-pin fineline bga ? device, the i/o pins u12 and u18 must be connected to ground. in the hc1s40 780-pin fineline bga device, the i/o pins u12 and u18 are available as general-purpose i/o pins. the bsdl file describes re-ordered joint test action group (jtag) boundary-scan chains. the jtag boundary-scan chain is defined in the bsdl file. note to table 2?1 : (1) performance and power consumption are design dependant. table 2?1. hardcopy stratix and stratix device comparison (part 2 of 2) hardcopy stratix stratix table 2?2. hardcopy stratix and stratix logic comparison hardcopy stratix stratix all routing connections are direct and all unused routing is removed. multitrack routing stitches routing resources together to provide a path. www.datasheet.in altera corporation 2?5 september 2008 description, architecture, and features although memory resource implementation is equivalent, the number of specific m-ram blocks are not necessarily the same between corresponding stratix and hardcopy stratix devices. table 2?3 shows the number of m-ram blocks available in each device. in hardcopy stratix devices, it is not possible to preload ram contents using a mif after powering up; the output registers of memory blocks will have unknown values. this occurs because there is no configuration process that is executed. 1 violating the setup or hold time requirements on address registers could corrupt the memory contents. this requirement applies to both read and write operations. table 2?4 illustrates the differences between hardcopy stratix and stratix memory. table 2?3. hardcopy stratix and stratix m-ram block comparison hardcopy stratix stratix device m-ram blocks device m-ram blocks hc1s25 2 ep1s25 2 hc1s30 2 ep1s30 4 hc1s40 2 ep1s40 4 HC1S60 6 ep1s60 6 hc1s830 6 ep1s830 9 table 2?4. hardcopy stratix and stratix memory comparison hardcopy stratix stratix hc1s30 and hc1s40 devices have two m-ram blocks. hc1s80 devices have six m-ram blocks. ep1s30 and ep1s40 devices have four m-ram blocks. ep1s80 devices have nine m-ram blocks. it is not possible to initialize m512 and m4k ram contents during power-up. the contents of m512 and m4k ram blocks can be preloaded during configuration with data specified in a mif. the contents of memory output registers are unknown after por. the contents of memory output registers are initialized to ?0? after por. www.datasheet.in 2?6 altera corporation september 2008 dsp blocks dsp blocks dsp blocks in hardcopy stratix devices are architecturally identical to those in stratix devices. the number of dsp blocks available in hardcopy stratix devices matches the number of dsp blocks available in the corresponding stratix device. plls and clock networks the plls in hardcopy stratix devices are identical to those in stratix devices. the clock networks are also implemented exactly as they are in stratix devices. the number of plls can vary between corresponding stratix and hardcopy stratix devices. ta b le 2 ?5 shows the number of plls available in each device. table 2?6 illustrates the differences between hardcopy stratix and stratix plls. i/o structure and features the hardcopy stratix ioes are equivalent, but not identical to, the stratix fpga ioes. this is due to the reduced die size, layout difference, and metal customization of the hardcopy stratix device. the differences are minor but may be relevant to customers designing with tight dc and switching characteristics. however, no signal integrity concerns are introduced with hardcopy stratix ioes. table 2?5. hardcopy stratix and stratix pll comparison hardcopy stratix stratix device plls device plls hc1s25 6 ep1s25 6 hc1s30 6 ep1s30 10 hc1s40 6 ep1s40 12 HC1S60 12 ep1s60 12 ep1s830 12 ep1s830 12 table 2?6. hardcopy stratix and stratix pll differences hardcopy stratix stratix hc1s30 and hc1s40 devices have six plls. hc1s30 devices have 10 plls. hc1s40 devices have12 plls. pll dynamic reconfiguration uses rom for information. this reconfiguration is performed in the back-end and does not affect the migration flow. pll dynamic reconfiguration uses a mif to initialize a ram resource with information. www.datasheet.in altera corporation 2?7 september 2008 description, architecture, and features when designing with very tight timing constraints (for example, ddr or quad data rate [qdr]), or if using the programmable drive strength option, altera recommends verifying final drive strength using updated ibis models located on the altera website at www.altera.com . differential i/o standards are unaffected. i/o pin placement and vref pin placement rules are identical between hardcopy stratix and stratix devices. unused pin settings will carry over from stratix device settings and are implemented as tri-stated outputs driving ground or outputs driving v cc . in stratix ep1s40 780-pin fineline bga fpgas, the i/o pins u12 and u18 are available as general-purpose i/o pins. in the fpga prototype, ep1s40f780_hardcopy_fpga_prototype, and in the hardcopy stratix hc1s40 780-pin fineline bga device, the i/o pins u12 and u18 must be connected to ground. hc1s40 780-pin fineline bga and ep1s40f780_hardcopy_fpga_prototype pin-outs are identical. table 2?7 illustrates the differences between hardcopy stratix and stratix i/o pins. power-up modes in hardcopy stratix devices designers do not need to configure hardcopy stratix devices, unlike their fpga counterparts. however, to facilitate seamless migration, configuration can be emulated in hardcopy stratix devices. the modes in which a hardcopy stratix device can be made ready for operation after power-up are: instant on, instant on after 50 ms, and configuration emulation. these modes are briefly described below. table 2?7. hardcopy stratix and stratix i/o pin comparison hardcopy stratix stratix the ioes are equivalent, but not identical to, the fpga ioes due to slight design optimizations for hardcopy devices. ioes are optimized for the fpga architecture. the i/o drive strength for single-ended i/o pins are slightly different and are found in the hardcopy stratix ibis models. the i/o drive strength for single-ended i/o pins are found in stratix ibis models. in the hc1s40 780-pin fineline bga device, the i/o pins u12 and u18 must be connected to ground. in the ep1s40 780-pin fineline bga device, the i/o pins u12 and u18 are available as general-purpose i/o pins. www.datasheet.in 2?8 altera corporation september 2008 hot socketing in instant on mode, the hardcopy stratix device is available for use shortly after the device receives power. the on-chip por circuit resets all registers. the conf_done output is tri-stated once the por has elapsed. no configuration device or configuration data is necessary. in instant on after 50 ms mode, the hardcopy stratix device performs in a fashion similar to the instant on mode, except that there is an additional delay of 50 ms, during which time the device is held in reset stage. the conf_done output is pulled low during this time, and then tri-stated after the 50 ms have elapsed. no configuration device or configuration data is necessary for this option. in configuration emulation mode, the hardcopy series device emulates the behavior of an apex or stratix fpga during its configuration phase. when this mode is used, the hardcopy device uses a configuration emulation circuit to receive configuration bit streams. when all the configuration data is received, the hardcopy series device transitions into an initialization phase and releases the conf_done pin to be pulled high. pulling the conf_done pin high signals that the hardcopy series device is ready for normal operation. if the optional open-drain init_done output is used, the normal operation is delayed until this signal is released by the hardcopy series device. 1 hardcopy ii and some hardcopy stratix devices do not support configuration emulation mode. instant on and instant on after 50 ms modes are the recommended power-up modes because these modes are similar to an asic?s functionality upon power-up. no changes to the existing board design or the configuration software are required. all three modes provide significant benefits to system designers. they enable seamless migration of the design from the fpga device to the hardcopy device with no changes to the existing board design or the configuration software. the pull-up resistors on n config , n status , and conf_done should be left on the printed circuit board. f for more information, refer to the hardcopy series configuration emulation chapter in the hardcopy series handbook . hot socketing hardcopy stratix devices support hot socketing without any external components. in a hot socketing situation, a device?s output buffers are turned off during system power up or power down. to simplify board design, hardcopy stratix devices support any power-up or power-down sequence (v ccio and v ccint ). for mixed-voltage environments, you can www.datasheet.in altera corporation 2?9 september 2008 description, architecture, and features drive signals into the device before or during power up or power down without damaging the device. hardcopy stratix devices do not drive out until they have attained proper operating conditions. you can power up or power down the v ccio and v ccint pins in any sequence. the power supply ramp rates can range from 100 ns to 100 ms. during hot socketing, the i/o pin capacitance is less than 15 pf and the clock pin capacitance is less than 20 pf. the hot socketing dc specification is | i iopin | < 300 a. the hot socketing ac specification is | i iopin | < 8 ma for 10 ns or less. this specification takes into account the pin capacitance only. additional capacitance for trace, connector, and loading needs to be taken into consideration separately. i iopin is the current at any user i/o pin on the device. 1 the dc specification applies when all v cc supplies to the device are stable in the powered-up or powered-down conditions. for the ac specification, the peak current duration due to power-up transients is 10 ns or less. hardcopy_ fpga_ prototype devices hardcopy_fpga_prototype devices are stratix fpgas available for designers to prototype their hardcopy stratix designs and perform in-system verification before migration to a hardcopy stratix device. the hardcopy_fpga_prototype devices have the same available resources as in the final hardcopy stratix devices. the quartus ii software version 4.1 and later contains the latest timing models. for designs with tight timing constraints, altera strongly recommends compiling the design with the quartus ii software version 4.1 or later. to properly verify i/o features, it is important to design with the hardcopy_fpga_prototype device option prior to migrating to a hardcopy stratix device. www.datasheet.in 2?10 altera corporation september 2008 document revision history 1 some hardcopy_fpga_prototype devices, as indicated in table 2?8 , have fewer m-ram blocks compared to the equivalent stratix fpgas. the selective removal of these resources provides a significant price benefit to designers using hardcopy stratix devices. f for more information about how the various features in the quartus ii software can be used for designing hardcopy stratix devices, refer to the quartus ii support for hardcopy stratix devices chapter of the hardcopy series handbook . hardcopy_fpga_prototype fpga devices have the identical speed grade as the equivalent stratix fpgas. however, hardcopy stratix devices are customized and do not have any speed grading. hardcopy stratix devices, on an average, can be 50% faster than their equivalent hardcopy_fpga_prototype devices. the actual improvement is design-dependent. document revision history table 2?9 shows the revision history for this chapter. table 2?8. m-ram block comparison between various devices number of les hardcopy_fpga_prototype devices hardcopy stratix devices stratix devices device m-ram blocks device m-ram blocks device m-ram blocks 25,660 ep1s25 2 hc1s25 2 ep1s25 2 32,470 ep1s30 2 hc1s30 2 ep1s30 4 41,250 ep1s40 2 hc1s40 2 ep1s40 4 57,120 ep1s60 6 HC1S60 6 ep1s60 6 79,040 ep1s830 6 hc1s830 6 ep1s830 9 table 2?9. document revision history (part 1 of 2) date and document version changes made summary of changes september 2008 v3.4 revised chapter number and metadata. ? june 2007 v3.3 updated table 2?1 . added note to the ?embedded memory? section. updated the ?hot socketing? section. ? www.datasheet.in altera corporation 2?11 september 2008 description, architecture, and features december 2006 v3.2 updated revision history. ? march 2006 formerly chapter 6; no content change. ? october 2005 v3.1 minor edits updated graphics minor edits. may 2005 v3.0 added table 6-1 added the logic elements section added the embedded memory section added the dsp blocks section added the plls and clock networks section added the i/o structure and features section minor update. january 2005 v2.0 added summary of i/o and timing differences between stratix fpgas and hardcopy stratix devices removed section on quartus ii support of hardcopy stratix devices added ?hot socketing? section minor update. august 2003 v1.1 edited section headings? hierarchy. minor edits. june 2003 v1.0 initial release of chapter 6, description, architecture and features, in the hardcopy device handbook ? table 2?9. document revision history (part 2 of 2) date and document version changes made summary of changes www.datasheet.in 2?12 altera corporation september 2008 document revision history www.datasheet.in altera corporation 3?1 september 2008 preliminary 3. boundary-scan support ieee std. 1149.1 (jtag) boundary-scan support all hardcopy ? stratix ? structured asics provide jtag boundry-scan test (bst) circuitry that complies with the ieee std. 1149.1-1990 specification. the bst architecture offers the capability to efficiently test components on printed circuit boards (pcbs) with tight lead spacing by testing pin connections, without using physical test probes, and capturing functional data while a device is in normal operation. boundary-scan cells in a device can force signals onto pins, or capture data from pin or core logic signals. forced test data is serially shifted into the boundary-scan cells. captured data is serially shifted out and externally compared to expected results. a device using the jtag interface uses four required pins, tdi , tdo , tms , and tck , and one optional pin, trst . hardcopy stratix devices support the jtag instructions as shown in table 3?1 . table 3?1. hardcopy stratix jtag instructions (part 1 of 2) jtag instruction instruction code description sample/preload 00 0000 0101 allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern to be output at the device pins. extest (1) 00 0000 0000 allows the external circuitry and board-level interconnects to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. bypass 11 1111 1111 places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices during normal device operation. usercode 00 0000 0111 selects the 32-bit usercode register and places it between the tdi and tdo pins, allowing the usercode to be serially shifted out of tdo . idcode 00 0000 0110 selects the idcode register and places it between tdi and tdo , allowing the idcode to be serially shifted out of tdo . highz (1) 00 0000 1011 places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices during normal device operation, while tri-stating all of the i/o pins. h51004-3.4 www.datasheet.in 3?2 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 f the boundary-scan description language (bsdl) files for hardcopy stratix devices are different from the corresponding stratix fpgas. the bsdl files for hardcopy stratix devices are available for download from the altera website at www.altera.com . the hardcopy stratix device instruction register length is 10 bits; the usercode register length is 32 bits. the usercode registers are mask-programmed, so they are not re-programmable. the designer can choose an appropriate 32-bit sequence to program into the usercode registers. tables 3?2 and 3?3 show the boundary-scan register length and device idcode information for hardcopy stratix devices. clamp (1) 00 0000 1010 places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices during normal device operation while holding i/o pins to a state defined by the data in the boundary-scan register. note to table 3?1 : (1) bus hold and weak pull-up resistor features override the high-impedance state of highz , clamp , and extest . table 3?1. hardcopy stratix jtag instructions (part 2 of 2) jtag instruction instruction code description table 3?2. hardcopy stratix boundary-scan register length device maximum boundary-scan register length hc1s25 672-pin fineline bga 1,458 hc1s30 780-pin fineline bga 1,878 hc1s40 780-pin fineline bga 1,878 HC1S60 1,020-pin fineline bga 2,382 hc1s80 1,020-pin fineline bga 2,382 www.datasheet.in altera corporation 3?3 september 2008 preliminary ieee std. 1149.1 (jtag) boundary-scan support figure 3?1 shows the timing requirements for the jtag signals. figure 3?1. hardcopy stratix jtag waveforms table 3?3. 32-bit hardcopy stratix device idcode device idcode (32 bits) (1) version (4 bits) part number (16 bits) manufacturer identity (11 bits) lsb (1 bit) (2) hc1s25 0000 0010 0000 0000 0011 000 0110 1110 1 hc1s30 0000 0010 0000 0000 0100 000 0110 1110 1 hc1s40 0000 0010 0000 0000 0101 000 0110 1110 1 HC1S60 0000 0010 0000 0000 0110 000 0110 1110 1 hc1s80 0000 0010 0000 0000 0111 000 0110 1110 1 notes to tab le 3 ?3 : (1) the most significant bit (msb) is on the left. (2) the idcode ?s least significant bit (lsb) is always 1. tdo tck t jpzx t jpco t jph t jpxz t jcp t jpsu t jcl t jch tdi tms signal to be captured signal to be driven t jszx t jssu t jsh t jsco t jsxz www.datasheet.in 3?4 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 table 3?4 shows the jtag timing parameters and values for hardcopy stratix devices. f for more information on jtag, refer to an 39: ieee std. 1149.1 (jtag) boundary-scan testing in altera devices . document revision history table 3?5 shows the revision history for this chapter. table 3?4. hardcopy stratix jtag timing parameters and values symbol parameter min max unit t jcp tck clock period 100 ns t jch tck clock high time 50 ns t jcl tck clock low time 50 ns t jpsu jtag port setup time 20 ns t jph jtag port hold time 45 ns t jpco jtag port clock to output 25 ns t jpzx jtag port high impedance to valid output 25 ns t jpxz jtag port valid output to high impedance 25 ns t jssu capture register setup time 20 ns t jsh capture register hold time 45 ns t jsco update register clock to output 35 ns t jszx update register high impedance to valid output 35 ns t jsxz update register valid output to high impedance 35 ns table 3?5. document revision history (part 1 of 2) date and document version changes made summary of changes september 2008 v3.4 updated chapter number and metadata. ? june 2007 v3.3 updated figure 3?1 .? december 2006 v3.2 updated revision history. ? march 2006 formerly chapter 7; no content change. ? www.datasheet.in altera corporation 3?5 september 2008 preliminary document revision history october 2005 v3.1 minor edits graphic updates ? may 2005 v3.0 updated ?ieee std. 1149.1 (jtag) boundary-scan support? section january 2005 v2.0 added information about usercode registers june 2003 v1.0 initial release of chapter 7, boundary-scan support, in the hardcopy device handbook table 3?5. document revision history (part 2 of 2) date and document version changes made summary of changes www.datasheet.in 3?6 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 www.datasheet.in altera corporation 4?1 september 2008 4. operating conditions recommended operating conditions tables 4?1 through 4?3 provide information on absolute maximum ratings, recommended operating conditions, dc operating conditions, and capacitance for 1.5-v hardcopy ? stratix ? devices. table 4?1. hardcopy stratix device absolute maximum ratings notes (1) , (2) symbol parameter conditions minimum maximum unit v ccint supply voltage with respect to ground ?0.5 2.4 v v ccio ?0.5 4.6 v v i dc input voltage (3) ?0.5 4.6 v i out dc output current, per pin ?25 40 ma t stg storage temperature no bias ?65 150 c t j junction temperature bga packages under bias 135 c table 4?2. hardcopy stratix device recommended operating conditions symbol parameter conditions minimum maximum unit v ccint supply voltage for internal logic and input buffers (4) 1.425 1.575 v v ccio supply voltage for output buffers, 3.3-v operation (4) , (5) 3.00 (3.135) 3.60 (3.465) v supply voltage for output buffers, 2.5-v operation (4) 2.375 2.625 v supply voltage for output buffers, 1.8-v operation (4) 1.71 1.89 v supply voltage for output buffers, 1.5-v operation (4) 1.4 1.6 v v i input voltage (3) , (6) ?0.5 4.1 v v o output voltage 0 v ccio v t j operating junction temperature for commercial use 0 85 c for industrial use ?40 100 c h51005-3.4 www.datasheet.in 4?2 altera corporation september 2008 recommended operating conditions table 4?3. hardcopy stratix device dc operating conditions note (7) symbol parameter conditions minimum typical maximum unit i i input pin leakage current v i = v cciomax to 0 v (8) ?10 10 a i oz tri-stated i/o pin leakage current v o = v cciomax to 0 v (8) ?10 10 a i cc0 v cc supply current (standby) (all memory blocks in power-down mode) v i = ground, no load, no toggling inputs ma r conf value of i/o pin pull-up resistor before and during configuration vi=0; v ccio = 3.3 v (9) 15 25 50 k vi=0; v ccio = 2.5 v (9) 20 45 70 k vi=0; v ccio = 1.8 v (9) 30 65 100 k vi=0; v ccio = 1.5 v (9) 50 100 150 k recommended value of i/o pin external pull-down resistor before and during configuration 12k notes to tables 4?1 through 4?3 : (1) refer to the operating requirements for altera devices data sheet. (2) conditions beyond those listed in ta b l e 4 ? 1 may cause permanent damage to a device. additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device. (3) minim um dc input is ?0.5 v. during transitions, the inputs may und ershoot to ?2 v or overshoot to 4.6 v for input currents less than 100 ma and periods shorter than 20 ns. (4) maximum v cc rise time is 100 ms, and v cc must rise monotonically. (5) v ccio maximum and minimum conditions for lvpecl, lvds, and 3.3-v pcml are shown in parentheses. (6) all pins, including dedicated inputs, clock, i/o, and jtag pins, may be driven before v cc int and v cc io are powered. (7) typical values are for t a = 25 c, v cc int = 1.5 v, and v cc io = 1.5 v, 1.8 v, 2.5 v, and 3.3 v. (8) this value is specified for normal device operation. the value may vary during power up. this applies for all v ccio settings (3.3, 2.5, 1.8, and 1.5 v). (9) pin pull-up resistance values will be lower if an external source drives the pin higher than v cc io . www.datasheet.in altera corporation 4?3 september 2008 operating conditions tables 4?4 through 4?31 list the dc operating specifications for the supported i/o standards. these tables list minimal specifications only; hardcopy stratix devices may exceed these specifications. table 4?32 provides information on capacitance for 1.5-v hardcopy stratix devices. table 4?4. lvttl specifications symbol parameter conditions minimum maximum unit v ccio output supply voltage 3.0 3.6 v v ih high-level input voltage 1.7 4.1 v v il low-level input voltage ?0.5 0.7 v v oh high-level output voltage i oh = ?4 to ?24 ma (1) 2.4 v v ol low-level output voltage i ol = 4 to 24 ma (1) 0.45 v table 4?5. lvcmos specifications symbol parameter conditions minimum maximum unit v ccio output supply voltage 3.0 3.6 v v ih high-level input voltage 1.7 4.1 v v il low-level input voltage ?0.5 0.7 v v oh high-level output voltage v ccio = 3.0, i oh = ?0.1 ma v ccio ? 0.2 v v ol low-level output voltage v ccio = 3.0, i ol = 0.1 ma 0.2 v table 4?6. 2.5-v i/o specifications symbol parameter conditions minimum maximum unit v ccio output supply voltage 2.375 2.625 v v ih high-level input voltage 1.7 4.1 v v il low-level input voltage ?0.5 0.7 v v oh high-level output voltage i oh = ?0.1 ma 2.1 v i oh = ?1 ma 2.0 v i oh = ?2 to ?16 ma (1) 1.7 v v ol low-level output voltage i ol = 0.1 ma 0.2 v i ol = 1 ma 0.4 v i ol = 2 to 16 ma (1) 0.7 v www.datasheet.in 4?4 altera corporation september 2008 recommended operating conditions table 4?7. 1.8-v i/o specifications symbol parameter conditions minimum maximum unit v ccio output supply voltage 1.65 1.95 v v ih high-level input voltage 0.65 v ccio 2.25 v v il low-level input voltage ?0.3 0.35 v ccio v v oh high-level output voltage i oh = ?2 to ?8 ma (1) v ccio ? 0.45 v v ol low-level output voltage i ol = 2 to 8 ma (1) 0.45 v table 4?8. 1.5-v i/o specifications symbol parameter conditions minimum maximum unit v ccio output supply voltage 1.4 1.6 v v ih high-level input voltage 0.65 v ccio v ccio + 0.3 v v il low-level input voltage ?0.3 0.35 v ccio v v oh high-level output voltage i oh = ?2 ma (1) 0.75 v ccio v v ol low-level output voltage i ol = 2 ma (1) 0.25 v ccio v table 4?9. 3.3-v lvds i/o specifications (part 1 of 2) symbol parameter conditions minimum typical maximum unit v ccio i/o supply voltage 3.135 3.3 3.465 v v id input differential voltage swing 0.1 v < v cm < 1.1 v j = 1 through 10 300 1,000 mv 1.1 v v cm 1.6 v j = 1 200 1,000 mv 1.1 v v cm 1.6 v j = 2 through10 100 1,000 mv 1.6 v < v cm < 1.8 v j = 1 through 10 300 1,000 mv www.datasheet.in altera corporation 4?5 september 2008 operating conditions v icm input common mode voltage lv ds 0.3 v < v id < 1.0 v j = 1 through 10 100 1,100 mv lv ds 0.3 v < v id < 1.0 v j = 1 through 10 1,600 1,800 mv lv ds 0.2 v < v id < 1.0 v j = 1 1,100 1,600 mv lv ds 0.1 v < v id < 1.0 v j = 2 through 10 1,100 1,600 mv v od (2) output differential voltage r l = 100 250 375 550 mv v od change in v od between high and low r l = 100 50 mv v ocm output common mode voltage r l = 100 1,125 1,200 1,375 mv v ocm change in v ocm between high and low r l = 100 50 mv r l receiver differential input resistor 90 100 110 table 4?9. 3.3-v lvds i/o specifications (part 2 of 2) symbol parameter conditions minimum typical maximum unit www.datasheet.in 4?6 altera corporation september 2008 recommended operating conditions table 4?10. 3.3-v pcml specifications symbol parameter conditions minimum typical maximum unit v ccio i/o supply voltage 3.135 3.3 3.465 v v id input differential voltage swing 300 600 mv v icm input common mode voltage 1.5 3.465 v v od output differential voltage 300 370 500 mv v od change in v od between high and low 50 mv v ocm output common mode voltage 2.5 2.85 3.3 v v ocm change in v ocm between high and low 50 mv v t output termination voltage v ccio v r 1 output external pull-up resistors 45 50 55 r 2 output external pull-up resistors 45 50 55 table 4?11. lvpecl specifications symbol parameter conditions minimum typical maximum unit v ccio i/o supply voltage 3.135 3.3 3.465 v v id input differential voltage swing 300 1,000 mv v icm input common mode voltage 12v v od output differential voltage r l = 100 525 700 970 mv v ocm output common mode voltage r l = 100 1.5 1.7 1.9 v r l receiver differential input resistor 90 100 110 www.datasheet.in altera corporation 4?7 september 2008 operating conditions table 4?12. hypertransport technology specifications symbol parameter conditions minimum typical maximum unit v ccio i/o supply voltage 2.375 2.5 2.625 v v id input differential voltage swing 300 900 mv v icm input common mode voltage 300 900 mv v od output differential voltage r l = 100 380 485 820 mv v od change in v od between high and low r l = 100 50 mv v ocm output common mode voltage r l = 100 440 650 780 mv v ocm change in v ocm between high and low r l = 100 50 mv r l receiver differential input resistor 90 100 110 table 4?13. 3.3-v pci specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 3.0 3.3 3.6 v v ih high-level input voltage 0.5 v ccio v ccio + 0.5 v v il low-level input voltage ?0.5 0.3 v ccio v v oh high-level output voltage i out = ?500 a0.9 v ccio v v ol low-level output voltage i out = 1,500 a0.1 v ccio v table 4?14. pci-x 1.0 specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 3.0 3.6 v v ih high-level input voltage 0.5 v ccio v ccio + 0.5 v v il low-level input voltage ?0.5 0.35 v ccio v v ipu input pull-up voltage 0.7 v ccio v v oh high-level output voltage i out = ?500 a0.9 v ccio v v ol low-level output voltage i out = 1,500 a0.1 v ccio v www.datasheet.in 4?8 altera corporation september 2008 recommended operating conditions table 4?15. gtl+ i/o specifications symbol parameter conditions minimum typical maximum unit v tt termination voltage 1.35 1.5 1.65 v v ref reference voltage 0.88 1.0 1.12 v v ih high-level input voltage v ref + 0.1 v v il low-level input voltage v ref ? 0.1 v v ol low-level output voltage i ol = 34 ma (1) 0.65 v table 4?16. gtl i/o specifications symbol parameter conditions minimum typical maximum unit v tt termination voltage 1.14 1.2 1.26 v v ref reference voltage 0.74 0.8 0.86 v v ih high-level input voltage v ref + 0.05 v v il low-level input voltage v ref ? 0.05 v v ol low-level output voltage i ol = 40 ma (1) 0.4 v table 4?17. sstl-18 class i specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.65 1.8 1.95 v v ref reference voltage 0.8 0.9 1.0 v v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v v ih(dc) high-level dc input voltage v ref + 0.125 v v il(dc) low-level dc input voltage v ref ? 0.125 v v ih(ac) high-level ac input voltage v ref + 0.275 v v il(ac) low-level ac input voltage v ref ? 0.275 v v oh high-level output voltage i oh = ?6.7 ma (1) v tt + 0.475 v v ol low-level output voltage i ol = 6.7 ma (1) v tt ? 0.475 v www.datasheet.in altera corporation 4?9 september 2008 operating conditions table 4?18. sstl-18 class ii specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.65 1.8 1.95 v v ref reference voltage 0.8 0.9 1.0 v v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v v ih(dc) high-level dc input voltage v ref + 0.125 v v il(dc) low-level dc input voltage v ref ? 0.125 v v ih(ac) high-level ac input voltage v ref + 0.275 v v il(ac) low-level ac input voltage v ref ? 0.275 v v oh high-level output voltage i oh = ?13.4 ma (1) v tt + 0.630 v v ol low-level output voltage i ol = 13.4 ma (1) v tt ? 0.630 v table 4?19. sstl-2 class i specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 2.375 2.5 2.625 v v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v v ref reference voltage 1.15 1.25 1.35 v v ih(dc) high-level dc input voltage v ref + 0.18 3.0 v v il(dc) low-level dc input voltage ?0.3 v ref ? 0.18 v v ih(ac) high-level ac input voltage v ref + 0.35 v v il(ac) low-level ac input voltage v ref ? 0.35 v v oh high-level output voltage i oh = ?8.1 ma (1) v tt + 0.57 v v ol low-level output voltage i ol = 8.1 ma (1) v tt ? 0.57 v table 4?20. sstl-2 class ii specifications (part 1 of 2) symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 2.375 2.5 2.625 v v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v www.datasheet.in 4?10 altera corporation september 2008 recommended operating conditions v ref reference voltage 1.15 1.25 1.35 v v ih(dc) high-level dc input voltage v ref + 0.18 v ccio + 0.3 v v il(dc) low-level dc input voltage ?0.3 v ref ? 0.18 v v ih(ac) high-level ac input voltage v ref + 0.35 v v il(ac) low-level ac input voltage v ref ? 0.35 v v oh high-level output voltage i oh = ?16.4 ma (1) v tt + 0.76 v v ol low-level output voltage i ol = 16.4 ma (1) v tt ? 0.76 v table 4?21. sstl-3 class i specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 3.0 3.3 3.6 v v tt termination voltage v ref ? 0.05 v ref v ref + 0.05 v v ref reference voltage 1.3 1.5 1.7 v v ih(dc) high-level dc input voltage v ref + 0.2 v ccio + 0.3 v v il(dc) low-level dc input voltage ?0.3 v ref ? 0.2 v v ih(ac) high-level ac input voltage v ref + 0.4 v v il(ac) low-level ac input voltage v ref ? 0.4 v v oh high-level output voltage i oh = ?8 ma (1) v tt + 0.6 v v ol low-level output voltage i ol = 8 ma (1) v tt ? 0.6 v table 4?22. sstl-3 class ii specifications (part 1 of 2) symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 3.0 3.3 3.6 v v tt termination voltage v ref ? 0.05 v ref v ref + 0.05 v v ref reference voltage 1.3 1.5 1.7 v table 4?20. sstl-2 class ii specifications (part 2 of 2) symbol parameter conditions minimum typical maximum unit www.datasheet.in altera corporation 4?11 september 2008 operating conditions v ih(dc) high-level dc input voltage v ref + 0.2 v ccio + 0.3 v v il(dc) low-level dc input voltage ?0.3 v ref ? 0.2 v v ih(ac) high-level ac input voltage v ref + 0.4 v v il(ac) low-level ac input voltage v ref ? 0.4 v v oh high-level output voltage i oh = ?16 ma (1) v tt + 0.8 v v ol low-level output voltage i ol = 16 ma (1) v tt ? 0.8 v table 4?23. 3.3-v agp 2 specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 3.15 3.3 3.45 v v ref reference voltage 0.39 v ccio 0.41 v ccio v v ih high-level input voltage (4) 0.5 v ccio v ccio + 0.5 v v il low-level input voltage (4) 0.3 v ccio v v oh high-level output voltage i out = ?0.5 ma 0.9 v ccio 3.6 v v ol low-level output voltage i out = 1.5 ma 0.1 v ccio v table 4?24. 3.3-v agp 1 specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 3.15 3.3 3.45 v v ih high-level input voltage (4) 0.5 v ccio v ccio + 0.5 v v il low-level input voltage (4) 0.3 v ccio v v oh high-level output voltage i out = ?0.5 ma 0.9 v ccio 3.6 v v ol low-level output voltage i out = 1.5 ma 0.1 v ccio v table 4?22. sstl-3 class ii specifications (part 2 of 2) symbol parameter conditions minimum typical maximum unit www.datasheet.in 4?12 altera corporation september 2008 recommended operating conditions table 4?25. 1.5-v hstl class i specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.4 1.5 1.6 v v ref input reference voltage 0.68 0.75 0.9 v v tt termination voltage 0.7 0.75 0.8 v v ih (dc) dc high-level input voltage v ref + 0.1 v v il (dc) dc low-level input voltage ?0.3 v ref ? 0.1 v v ih (ac) ac high-level input voltage v ref + 0.2 v v il (ac) ac low-level input voltage v ref ? 0.2 v v oh high-level output voltage i oh = 8 ma (1) v ccio ? 0.4 v v ol low-level output voltage i oh = ?8 ma (1) 0.4 v table 4?26. 1.5-v hstl class ii specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.4 1.5 1.6 v v ref input reference voltage 0.68 0.75 0.9 v v tt termination voltage 0.7 0.75 0.8 v v ih (dc) dc high-level input voltage v ref + 0.1 v v il (dc) dc low-level input voltage ?0.3 v ref ? 0.1 v v ih (ac) ac high-level input voltage v ref + 0.2 v v il (ac) ac low-level input voltage v ref ? 0.2 v v oh high-level output voltage i oh = 16 ma (1) v ccio ? 0.4 v v ol low-level output voltage i oh = ?16 ma (1) 0.4 v www.datasheet.in altera corporation 4?13 september 2008 operating conditions table 4?27. 1.8-v hstl class i specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.65 1.80 1.95 v v ref input reference voltage 0.70 0.90 0.95 v v tt termination voltage v ccio 0.5 v v ih (dc) dc high-level input voltage v ref + 0.1 v v il (dc) dc low-level input voltage ?0.5 v ref ? 0.1 v v ih (ac) ac high-level input voltage v ref + 0.2 v v il (ac) ac low-level input voltage v ref ? 0.2 v v oh high-level output voltage i oh = 8 ma (1) v ccio ? 0.4 v v ol low-level output voltage i oh = ?8 ma (1) 0.4 v table 4?28. 1.8-v hstl class ii specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.65 1.80 1.95 v v ref input reference voltage 0.70 0.90 0.95 v v tt termination voltage v ccio 0.5 v v ih (dc) dc high-level input voltage v ref + 0.1 v v il (dc) dc low-level input voltage ?0.5 v ref ? 0.1 v v ih (ac) ac high-level input voltage v ref + 0.2 v v il (ac) ac low-level input voltage v ref ? 0.2 v v oh high-level output voltage i oh = 16 ma (1) v ccio ? 0.4 v v ol low-level output voltage i oh = ?16 ma (1) 0.4 v www.datasheet.in 4?14 altera corporation september 2008 recommended operating conditions table 4?29. 1.5-v differential hstl specifications symbol parameter conditions minimum typical maximum unit v ccio i/o supply voltage 1.4 1.5 1.6 v v dif (dc) dc input differential voltage 0.2 v v cm (dc) dc common mode input voltage 0.68 0.9 v v dif (ac) ac differential input voltage 0.4 v table 4?30. ctt i/o specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 2.05 3.3 3.6 v v tt /v ref termination and input reference voltage 1.35 1.5 1.65 v v ih high-level input voltage v ref + 0.2 v v il low-level input voltage v ref ? 0.2 v v oh high-level output voltage i oh = ?8 ma v ref + 0.4 v v ol low-level output voltage i ol = 8 ma v ref ? 0.4 v i o output leakage current (when output is high z ) gnd v out v ccio ?10 10 a table 4?31. bus hold parameters parameter conditions v ccio level unit 1.5 v1.8 v2.5 v3.3 v min max min max min max min max low sustaining current v in > v il (maximum) 25 30 50 70 a high sustaining current v in < v ih (minimum) ?25 ?30 ?50 ?70 a low overdrive current 0 v < v in < v ccio 160 200 300 500 a high overdrive current 0 v < v in < v ccio ?160 ?200 ?300 ?500 a bus hold trip point 0.5 1.0 0.68 1.07 0.7 1.7 0.8 2.0 v www.datasheet.in altera corporation 4?15 september 2008 operating conditions power consumption altera offers two ways to calculate power for a design, the altera ? web power calculator and the power estimation feature in the quartus ? ii software. the interactive power calculator on the altera website is typically used prior to designing the fpga in order to get a magnitude estimate of the device power. the quartus ii software power estimation feature allows designers to apply test vectors against their design for more accurate power consumption modeling. in both cases, these calculations should only be used as an estimation of power, not as a specification. timing closure the timing numbers in tables 4?34 to 4?43 are only provided as an indication of allowable timing for hardcopy stratix devices. the quartus ii software provides preliminary timing information for hardcopy stratix designs, which can be used as an estimation of the device performance. table 4?32. stratix device capacitance note (5) symbol parameter minimum typical maximum unit c iotb input capacitance on i/o pins in i/o banks 3, 4, 7, and 8. 11.5 pf c iolr input capacitance on i/o pins in i/o banks 1, 2, 5, and 6, including high-speed differential receiver and transmitter pins. 8.2 pf c clktb input capacitance on top/bottom clock input pins: clk[4..7] and clk[12..15] . 11.5 pf c clklr input capacitance on left/right clock inputs: clk1 , clk3 , clk8 , clk10 . 7.8 pf c clklr+ input capacitance on left/right clock inputs: clk0 , clk2 , clk9 , and clk11 . 4.4 pf notes to tables 4?4 through 4?32 : (1) drive strength is programmable according to values in the stratix architecture chapter of the stratix device handbook . (2) whe n the tx_outclock port of the altlvds_tx megafunction is 717 mhz, v od(min) = 235 mv on the output clock pin. (3) pin pull-up resistance values will lower if an external source drives the pin higher than v ccio . (4) v ref specifies the center point of the switching range. (5) capacitance is sample-tested only. capacitance is measured using time-domain reflections (tdr). measurement accuracy is within 0.5 pf. www.datasheet.in 4?16 altera corporation september 2008 timing closure the final timing numbers and actual performance for each hardcopy stratix design is available when the design migration is complete and are subject to verification and approval by altera and the designer during the hardcopy desi gn review process. f for more information, refer to the hardcopy series back-end timing closure chapter in the hardcopy series handbook . external timing parameters external timing parameters are specified by device density and speed grade. figure 4?1 shows the pin-to-pin timing model for bidirectional ioe pin timing. all registers are within the ioe. figure 4?1. external timing in hardcopy stratix devices all external timing parameters reported in this section are defined with respect to the dedicated clock pin as the starting point. all external i/o timing parameters shown are for 3.3-v lvttl i/o standard with the 4-ma current strength and fast slew rate. for external i/o timing using standards other than lvttl or for different current strengths, use the i/o standard input and output delay adders in the stratix device handbook . prn clrn dq oe register prn clrn dq input register prn clrn dq output register bidirectional pin dedicated clock t insu t inh t outco t xz t zx www.datasheet.in altera corporation 4?17 september 2008 operating conditions table 4?33 shows the external i/o timing parameters when using global clock networks. hardcopy stratix external i/o timing these timing parameters are for both column ioe and row ioe pins. in hc1s30 devices and above, designers can decrease the t su time by using fpllclk , but may get positive hold time in HC1S60 and hc1s80 devices. designers should use the quartus ii software to verify the external devices for any pin. table 4?33. hardcopy stratix global clock external i/o timing parameters notes (1) , (2) symbol parameter t insu setup time for input or bidirectional pin using ioe input register with global clock fed by clk pin t inh hold time for input or bidirectional pin using ioe input register with global clock fed by clk pin t outco clock-to-output delay output or bidirectional pin using ioe output register with global clock fed by clk pin t insupll setup time for input or bidirectional pin using ioe input register with global clock fed by enhanced pll with default phase setting t inhpll hold time for input or bidirectional pin using ioe input register with global clock fed by enhanced pll with default phase setting t outcopll clock-to-output delay output or bidirectional pin using ioe output register with global clock enhanced pll with default phase setting t xzpll synchronous ioe output enable register to output pin disable delay using global clock fed by enhanced pll with default phase setting t zxpll synchronous ioe output enable register to output pin enable delay using global clock fed by enhanced pll with default phase setting notes to tab le 4 ?3 3 : (1) these timing parameters are sample-tested only. (2) these timing parameters are for column and row ioe pins. designers should use the quartus ii software to verify the external timing for any pin. www.datasheet.in 4?18 altera corporation september 2008 timing closure tables 4?34 through 4?35 show the external timing parameters on column and row pins for hc1s25 devices. table 4?34. hc1s25 external i/o timing on column pins using global clock networks parameter performance unit min max t insu 1.371 ns t inh 0.000 ns t outco 2.809 7.155 ns t xz 2.749 7.040 ns t zx 2.749 7.040 ns t insupll 1.271 ns t inhpll 0.000 ns t outcopll 1.124 2.602 ns t xzpll 1.064 2.487 ns t zxpll 1.064 2.487 ns table 4?35. hc1s25 external i/o timing on row pins using global clock networks parameter performance unit min max t insu 1.665 ns t inh 0.000 ns t outco 2.834 7.194 ns t xz 2.861 7.276 ns t zx 2.861 7.276 ns t insupll 1.538 ns t inhpll 0.000 ns t outcopll 1.164 2.653 ns t xzpll 1.191 2.735 ns t zxpll 1.191 2.735 ns www.datasheet.in altera corporation 4?19 september 2008 operating conditions tables 4?36 through 4?37 show the external timing parameters on column and row pins for hc1s30 devices. table 4?36. hc1s30 external i/o timing on column pins using global clock networks parameter performance unit min max t insu 1.935 ns t inh 0.000 ns t outco 2.814 7.274 ns t xz 2.754 7.159 ns t zx 2.754 7.159 ns t insupll 1.265 ns t inhpll 0.000 ns t outcopll 1.068 2.423 ns t xzpll 1.008 2.308 ns t zxpll 1.008 2.308 ns table 4?37. hc1s30 external i/o timing on row pins using global clock networks parameter performance unit min max t insu 1.995 ns t inh 0.000 ns t outco 2.917 7.548 ns t xz 2.944 7.630 ns t zx 2.944 7.630 ns t insupll 1.337 ns t inhpll 0.000 ns t outcopll 1.164 2.672 ns t xzpll 1.191 2.754 ns t zxpll 1.191 2.754 ns www.datasheet.in 4?20 altera corporation september 2008 timing closure tables 4?38 through 4?39 show the external timing parameters on column and row pins for hc1s40 devices. table 4?38. hc1s40 external i/o timing on column pins using global clock networks parameter performance unit min max t insu 2.126 ns t inh 0.000 ns t outco 2.856 7.253 ns t xz 2.796 7.138 ns t zx 2.796 7.138 ns t insupll 1.466 ns t inhpll 0.000 ns t outcopll 1.092 2.473 ns t xzpll 1.032 2.358 ns t zxpll 1.032 2.358 ns table 4?39. hc1s40 external i/o timing on row pins using global clock networks parameter performance unit min max t insu 2.020 ns t inh 0.000 ns t outco 2.912 7.480 ns t xz 2.939 7.562 ns t zx 2.939 7.562 ns t insupll 1.370 ns t inhpll 0.000 ns t outcopll 1.144 2.693 ns t xzpll 1.171 2.775 ns t zxpll 1.171 2.775 ns www.datasheet.in altera corporation 4?21 september 2008 operating conditions tables 4?40 through 4?41 show the external timing parameters on column and row pins for HC1S60 devices. table 4?40. HC1S60 external i/o timing on column pins using global clock networks parameter performance unit min max t insu 2.000 ns t inh 0.000 ns t outco 3.051 6.977 ns t xz 2.991 6.853 ns t zx 2.991 6.853 ns t insupll 1.315 ns t inhpll 0.000 ns t outcopll 1.029 2.323 ns t xzpll 0.969 2.199 ns t zxpll 0.969 2.199 ns table 4?41. HC1S60 external i/o timing on row pins using global clock networks parameter performance unit min max t insu 2.232 ns t inh 0.000 ns t outco 3.182 7.286 ns t xz 3.209 7.354 ns t zx 3.209 7.354 ns t insupll 1.651 ns t inhpll 0.000 ns t outcopll 1.154 2.622 ns t xzpll 1.181 2.690 ns t zxpll 1.181 2.690 ns www.datasheet.in 4?22 altera corporation september 2008 timing closure tables 4?42 through 4?43 show the external timing parameters on column and row pins for hc1s80 devices. table 4?42. hc1s80 external i/o timing on column pins using global clock networks parameter performance unit min max t insu 0.884 ns t inh 0.000 ns t outco 3.267 7.415 ns t xz 3.207 7.291 ns t zx 3.207 7.291 ns t insupll 0.506 ns t inhpll 0.000 ns t outcopll 1.635 2.828 ns t xzpll 1.575 2.704 ns t zxpll 1.575 2.704 ns table 4?43. hc1s80 external i/o timing on rows using pin global clock networks symbol performance unit min max t insu 1.362 ns t inh 0.000 ns t outco 3.457 7.859 ns t xz 3.484 7.927 ns t zx 3.484 7.927 ns t insupll 0.994 ns t inhpll 0.000 ns t outcopll 1.821 3.254 ns t xzpll 1.848 3.322 ns t zxpll 1.848 3.322 ns www.datasheet.in altera corporation 4?23 september 2008 operating conditions maximum input and output clock rates tables 4?44 through 4?46 show the maximum input clock rate for column and row pins in hardcopy stratix devices. table 4?44. hardcopy stratix maximum input clock rate for clk[7..4] and clk[15..12] pins i/o standard performance unit lvttl 422 mhz 2.5 v 422 mhz 1.8 v 422 mhz 1.5 v 422 mhz lvcmos 422 mhz gtl 300 mhz gtl+ 300 mhz sstl-3 class i 400 mhz sstl-3 class ii 400 mhz sstl-2 class i 400 mhz sstl-2 class ii 400 mhz sstl-18 class i 400 mhz sstl-18 class ii 400 mhz 1.5-v hstl class i 400 mhz 1.5-v hstl class ii 400 mhz 1.8-v hstl class i 400 mhz 1.8-v hstl class ii 400 mhz 3.3-v pci 422 mhz 3.3-v pci-x 1.0 422 mhz compact pci 422 mhz agp 1 422 mhz agp 2 422 mhz ctt 300 mhz differential hstl 400 mhz lv pe cl (1) 645 mhz pcml (1) 300 mhz lv ds (1) 645 mhz hypertransport technology (1) 500 mhz www.datasheet.in 4?24 altera corporation september 2008 timing closure table 4?45. hardcopy stratix maximum input clock rate for clk[0, 2, 9, 11] pins and fpll[10..7]clk pins i/o standard performance unit lvttl 422 mhz 2.5 v 422 mhz 1.8 v 422 mhz 1.5 v 422 mhz lvcmos 422 mhz gtl 300 mhz gtl+ 300 mhz sstl-3 class i 400 mhz sstl-3 class ii 400 mhz sstl-2 class i 400 mhz sstl-2 class ii 400 mhz sstl-18 class i 400 mhz sstl-18 class ii 400 mhz 1.5-v hstl class i 400 mhz 1.5-v hstl class ii 400 mhz 1.8-v hstl class i 400 mhz 1.8-v hstl class ii 400 mhz 3.3-v pci 422 mhz 3.3-v pci-x 1.0 422 mhz compact pci 422 mhz agp 1 422 mhz agp 2 422 mhz ctt 300 mhz differential hstl 400 mhz lv pe cl (1) 717 mhz pcml (1) 400 mhz lv ds (1) 717 mhz hypertransport technology (1) 717 mhz www.datasheet.in altera corporation 4?25 september 2008 operating conditions table 4?46. hardcopy stratix maximum input clock rate for clk[1, 3, 8, 10] pins i/o standard performance unit lvttl 422 mhz 2.5 v 422 mhz 1.8 v 422 mhz 1.5 v 422 mhz lvcmos 422 mhz gtl 300 mhz gtl+ 300 mhz sstl-3 class i 400 mhz sstl-3 class ii 400 mhz sstl-2 class i 400 mhz sstl-2 class ii 400 mhz sstl-18 class i 400 mhz sstl-18 class ii 400 mhz 1.5-v hstl class i 400 mhz 1.5-v hstl class ii 400 mhz 1.8-v hstl class i 400 mhz 1.8-v hstl class ii 400 mhz 3.3-v pci 422 mhz 3.3-v pci-x 1.0 422 mhz compact pci 422 mhz agp 1 422 mhz agp 2 422 mhz ctt 300 mhz differential hstl 400 mhz lv pe cl (1) 645 mhz pcml (1) 300 mhz lv ds (1) 645 mhz hypertransport technology (1) 500 mhz note to tables 4?44 through 4?46 : (1) these parameters are only available on row i/o pins. www.datasheet.in 4?26 altera corporation september 2008 timing closure tables 4?47 through 4?48 show the maximum output clock rate for column and row pins in hardcopy stratix devices. table 4?47. hardcopy stratix maximum output clock rate for pll[5, 6, 11, 12] pins (part 1 of 2) i/o standard performance unit lvttl 350 mhz 2.5 v 350 mhz 1.8 v 250 mhz 1.5 v 225 mhz lvcmos 350 mhz gtl 200 mhz gtl+ 200 mhz sstl-3 class i 200 mhz sstl-3 class ii 200 mhz sstl-2 class i (3) 200 mhz sstl-2 class i (4) 200 mhz sstl-2 class i (5) 150 mhz sstl-2 class ii (3) 200 mhz sstl-2 class ii (4) 200 mhz sstl-2 class ii (5) 150 mhz sstl-18 class i 150 mhz sstl-18 class ii 150 mhz 1.5-v hstl class i 250 mhz 1.5-v hstl class ii 225 mhz 1.8-v hstl class i 250 mhz 1.8-v hstl class ii 225 mhz 3.3-v pci 350 mhz 3.3-v pci-x 1.0 350 mhz compact pci 350 mhz agp 1 350 mhz agp 2 350 mhz ctt 200 mhz differential hstl 225 mhz differential sstl-2 (6) 200 mhz lv pe cl (2) 500 mhz pcml (2) 350 mhz www.datasheet.in altera corporation 4?27 september 2008 operating conditions lv ds (2) 500 mhz hypertransport technology (2) 350 mhz table 4?48. hardcopy stratix maximum output clock rate (using i/o pins) for pll[1, 2, 3, 4] pins (part 1 of 2) i/o standard performance unit lvttl 400 mhz 2.5 v 400 mhz 1.8 v 400 mhz 1.5 v 350 mhz lvcmos 400 mhz gtl 200 mhz gtl+ 200 mhz sstl-3 class i 167 mhz sstl-3 class ii 167 mhz sstl-2 class i 150 mhz sstl-2 class ii 150 mhz sstl-18 class i 150 mhz sstl-18 class ii 150 mhz 1.5-v hstl class i 250 mhz 1.5-v hstl class ii 225 mhz 1.8-v hstl class i 250 mhz 1.8-v hstl class ii 225 mhz 3.3-v pci 250 mhz 3.3-v pci-x 1.0 225 mhz compact pci 400 mhz agp 1 400 mhz agp 2 400 mhz ctt 300 mhz differential hstl 225 mhz lv pe cl (2) 717 mhz pcml (2) 420 mhz table 4?47. hardcopy stratix maximum output clock rate for pll[5, 6, 11, 12] pins (part 2 of 2) i/o standard performance unit www.datasheet.in 4?28 altera corporation september 2008 high-speed i/o specification high-speed i/o specification table 4?49 provides high-speed timing specifications definitions. lv ds (2) 717 mhz hypertransport technology (2) 420 mhz notes to tables 4?47 through 4?48 : (1) differential sstl-2 outputs are only available on column clock pins. (2) these parameters are only available on row i/o pins. (3) sstl-2 in maximum drive strength condition. (4) sstl-2 in minimum drive strength with 10pf output load condition. (5) sstl-2 in minimum drive strength with > 10pf output load condition. (6) differential sstl-2 outputs are only supported on column clock pins. table 4?48. hardcopy stratix maximum output clock rate (using i/o pins) for pll[1, 2, 3, 4] pins (part 2 of 2) i/o standard performance unit table 4?49. high-speed timing specifications and terminology high-speed timing specification terminology t c high-speed receiver/transmitter input and output clock period. f hsclk high-speed receiver/transmitter input and output clock frequency. t rise low-to-high transmission time. t fa ll high-to-low transmission time. timing unit interval (tui) the timing budget allowed for skew, propagation delays, and data sampling window. (tui = 1/(receiver input clock frequency multiplication factor) = t c / w ). f hsdr maximum lvds data transfer rate (f hsdr = 1/tui). channel-to-channel skew (tccs) the timing difference between the fastest and slowest output edges, including t co variation and clock skew. the clock is included in the tccs measurement. sampling window (sw) the period of time during which the data must be valid to be captured correctly. the setup and hold times determine the ideal strobe position within the sampling window. sw = t sw (max) ? t sw (min). input jitter (peak-to-peak) peak-to-peak input jitter on high-speed plls. output jitter (peak-to-peak) peak-to-peak output jitter on high-speed plls. t duty duty cycle on high-speed transmitter output clock. t lock lock time for high-speed transmitter and receiver plls. www.datasheet.in altera corporation 4?29 september 2008 operating conditions table 4?50 shows the high-speed i/o timing for hardcopy stratix devices. table 4?50. high-speed i/o specifications (part 1 of 2) notes (1) , (2) symbol conditions performance unit min typ max f hsclk (clock frequency) (lvds, lvpecl, hypertransport technology) f hsclk = f hsdr / w w = 4 to 30 (serdes used) 10 210 mhz w = 2 (serdes bypass) 50 231 mhz w = 2 (serdes used) 150 420 mhz w = 1 (serdes bypass) 100 462 mhz w = 1 (serdes used) 300 717 mhz f hsdr device operation (lvds, lvpecl, hypertransport technology) j = 10 300 840 mbps j = 8 300 840 mbps j = 7 300 840 mbps j = 4 300 840 mbps j = 2 100 462 mbps j = 1 (lvds and lvpecl only) 100 462 mbps f hsclk (clock frequency) (pcml) f hsclk = f hsdr / w w = 4 to 30 (serdes used) 10 100 mhz w = 2 (serdes bypass) 50 200 mhz w = 2 (serdes used) 150 200 mhz w = 1 (serdes bypass) 100 250 mhz w = 1 (serdes used) 300 400 mhz f hsdr device operation (pcml) j = 10 300 400 mbps j = 8 300 400 mbps j = 7 300 400 mbps j = 4 300 400 mbps j = 2 100 400 mbps j = 1 100 250 mbps tccs all 200 ps sw pcml ( j = 4, 7, 8, 10) 750 ps pcml ( j = 2) 900 ps pcml ( j = 1) 1,500 ps lvds and lvpecl ( j = 1) 500 ps lv ds , lvp e cl , hypertransport technology ( j = 2 through 10) 440 ps www.datasheet.in 4?30 altera corporation september 2008 pll specifications pll specifications table 4?51 describes the hardcopy stratix device enhanced pll specifications. input jitter tolerance (peak-to-peak) all 250 ps output jitter (peak-to-peak) all 160 ps output t rise lvds 80 110 120 ps hypertransport technology 110 170 200 ps lvpecl 90 130 150 ps pcml 80 110 135 ps output t fall lvds 80 110 120 ps hypertransport technology 110 170 200 ps lvpecl 90 130 160 ps pcml 105 140 175 ps t duty lv ds ( j = 2 through 10) 47.5 50 52.5 % lv ds ( j =1) and lvpecl, pcml, hypertransport technology 45 50 55 % t lock all 100 s notes to tab le 4 ?5 0 : (1) whe n j = 4, 7, 8, and 10, the serdes block is used. (2) whe n j = 2 or j = 1, the serdes is bypassed. table 4?50. high-speed i/o specifications (part 2 of 2) notes (1) , (2) symbol conditions performance unit min typ max table 4?51. enhanced pll specifications (part 1 of 3) symbol parameter min typ max unit f in input clock frequency 3 (1) 684 mhz f induty input clock duty cycle 40 60 % f einduty external feedback clock input duty cycle 40 60 % t injitter input clock period jitter 200 (2) ps t einjitter external feedback clock period jitter 200 (2) ps t fcomp external feedback clock compensation time (3) 6ns www.datasheet.in altera corporation 4?31 september 2008 operating conditions f out output frequency for internal global or regional clock 0.3 500 mhz f out_ext output frequency for external clock (2) 0.3 526 mhz t outduty duty cycle for external clock output (when set to 50 % ) 45 55 % t jitter period jitter for external clock output (5) 100 ps for >200 mhz outclk 20 mui for <200 mhz outclk ps or mui t config5,6 time required to reconfigure the scan chains for plls 5 and 6 289/f scanclk t config11,12 time required to reconfigure the scan chains for plls 11 and 12 193/f scanclk t scanclk scanclk frequency (4) 22 mhz t dlock time required to lock dynamically (after switchover or reconfiguring any non- post-scale counters/delays) (6) (8) 100 s t lock time required to lock from end of device configuration 10 400 s f vco pll internal vco operating range 300 800 (7) mhz t lskew clock skew between two external clock outputs driven by the same counter 50 ps t skew clock skew between two external clock outputs driven by the different counters with the same settings 75 ps f ss spread spectrum modulation frequency 30 150 khz % spread percentage spread for spread spectrum frequency (9) 0.4 0.5 0.6 % table 4?51. enhanced pll specifications (part 2 of 3) symbol parameter min typ max unit www.datasheet.in 4?32 altera corporation september 2008 pll specifications t areset minimum pulse width on areset signal 10 (11) ns 500 (12) ns notes to tab le 4 ?5 1 : (1) the minimum input clock frequency to the pfd (f in / n ) must be at least 3 mhz for hardcopy stratix device enhanced plls. (2) refer to ?maximum input and output clock rates?. (3) t fc om p can also equal 50 % of the input clock period multiplied by the pre-scale divider n (whichever is less). (4) this parameter is timing analyzed by the quartus ii software because the scanclk and scandata ports can be driven by the logic array. (5) actual jitter performance may vary based on the system configuration. (6) total required time to reconfigure and lock is equal to t dlock + t config . if only post-scale counters and delays are changed, then t dlock is equal to 0. (7) the vco range is limited to 500 to 800 mhz when the spread spectrum feature is selected. (8) lock time is a function of pll configuration and may be significantly faster depending on bandwidth settings or feedback counter change increment. (9) exact, user-controllable value depends on the pll settings. (10) the lock circuit on hardcopy stratix plls does not work for industrial devices below ?20c unless the pfd frequency > 200 mhz. refer to the stratix fpga errata sheet for more information on the pll. (11) applicable when the pll input clock has been running continuously for at least 10 s. (12) applicable when the pll input clock has stopped toggling or has been running continuously for less than 10 s. table 4?51. enhanced pll specifications (part 3 of 3) symbol parameter min typ max unit www.datasheet.in altera corporation 4?33 september 2008 operating conditions table 4?52 describes the hardcopy stratix device fast pll specifications. electrostatic discharge electrostatic discharge (esd) protection is a design practice that is integrated in altera fpgas and structured asic devices. hardcopy stratix devices are no exception, and they are designed with esd protection on all i/o and power pins. table 4?52. fast pll specifications symbol parameter min max unit f in clkin frequency (for m = 1) (1) , (2) 300 717 mhz clkin frequency (for m = 2 to 19) 300/ m 1,000/ m mhz clkin frequency (for m = 20 to 32) 10 1,000/ m mhz f out output frequency for internal global or regional clock (3) 9.4 420 mhz f out_ext output frequency for external clock (2) 9.375 717 mhz f vco vco operating frequency 300 1,000 mhz t induty clkin duty cycle 40 60 % t injitter period jitter for clkin pin 200 ps t duty duty cycle for dffio 1 clkout pin (4) 45 55 % t jitter period jitter for dffio clock out (4) 80 ps period jitter for internal global or regional clock 100 ps for >200-mhz outclk 20 mui for <200-mhz outclk ps or mui t lock time required for pll to acquire lock 10 100 s m multiplication factors for m counter (4) 1 32 integer l 0, l 1, g 0 multiplication factors for l 0, l 1, and g 0 counter (5) , (6) 1 32 integer t areset minimum pulse width on areset signal 10 ns notes to tab le 4 ?5 2 : (1) refer to ?maximum input and output clock rates? on page 4?23 for more information. (2) plls 7, 8, 9, and 10 in the hc1s80 device support up to 717-mhz input and output. (3) when using the serdes, high-speed differential i/o mode supports a maximum output frequency of 210 mhz to the global or regional clocks (for example, the maximum data rate 840 mbps divided by the smallest serdes j factor of 4). (4) this parameter is for high-speed differential i/o mode only. (5) these counters have a maximum of 32 if programmed for 50/50 duty cycle. otherwise, they have a maximum of 16. (6) high-speed differential i/o mode supports w = 1 to 16 and j = 4, 7, 8, or 10. www.datasheet.in 4?34 altera corporation september 2008 electrostatic discharge figure 4?2 shows a transistor level cross section of the hardcopy stratix cmos i/o buffer structure which will be used to explain esd protection. figure 4?2. transistor-level cross section of the hardcopy stratix device i/o buffers the cmos output drivers in the i/o pins intrinsically provide electrostatic discharge protection. there are two cases to consider for esd voltage strikes: positive voltage zap and negative voltage zap. positive voltage zap a positive esd voltage zap occurs when a positive voltage is present on an i/o pin due to an esd charge event. this can cause the n+ (drain)/p- substrate) junction of the n-channel drain to break down and the n+ (drain)/p-substrate/n+ (source) intrinsic bipolar transistor turns on to discharge esd current from i/o pin to gnd. core signal vpad core signal or the larger of vccio or vpad vccio the larger of vccio or vpad ensures 3 v tolerance and hot-insertion protection n+ p-substrate p+ p+ n+ n+ p-well n-well www.datasheet.in altera corporation 4?35 september 2008 operating conditions the dashed line ( figure 4?3 ) shows the esd current discharge path during a positive voltage zap. figure 4?3. esd protection during positive voltage zap negative voltage zap when the i/o pin receives a negative esd zap at the pin that is less than -0.7 v (0.7 v is the voltage drop across a diode), the intrinsic psubstrate/n+ drain diode is forward biased. hence, the discharge esd current path is from gnd to the i/o pin, as shown in figure 4?4 . source gate gate pmos drain drain io source gnd io n+ d p-substrate n+ gnd s g nmos www.datasheet.in 4?36 altera corporation september 2008 document revision history the dashed line ( figure 4?4 ) shows the esd current discharge path during a negative voltage zap. figure 4?4. esd protection during negative voltage zap f details of esd protection are also outlined in the hot-socketing and power-sequencing feature and testing for altera devices white paper located on the altera website at www.altera.com . f for information on esd results of altera products, see the reliability report on the altera website at www.altera.com . document revision history table 4?53 shows the revision history for this chapter. source gate gate pmos drain drain io source gnd io n+ d p-substrate n+ gnd s g nmos table 4?53. document revision history (part 1 of 2) date and document version changes made summary of changes september 2008 v3.4 updated the revision history. ? june 2007 v3.3 updated r conf section of table 4?3 . added the ?electrostatic discharge? section. ? www.datasheet.in altera corporation 4?37 september 2008 operating conditions december 2006 v3.2 updated chapter number and metadata. ? march 2006 formerly chapter 8; no content change. ? october 2005 v3.1 minor edits graphic updates may 2005 v3.0 updated sstl-2 and sstl-3 specifications in tables 8?19 through 8?22 updated ctt i/o specifications in table 8?30 updated bus hold parameters in table 8?31. added the external timing parameters, hardcopy stratix external i/o timing, and maximum input and output clock rates sections added the high-speed i/o specification, and pll specifications sections ? january 2005 v2.0 removed recommended maximum rise and fall times (t r and t f ) for input signals ? june 2003 v1.0 initial release of chapter 8, operating conditions, in the hardcopy device handbook table 4?53. document revision history (part 2 of 2) date and document version changes made summary of changes www.datasheet.in 4?38 altera corporation september 2008 document revision history www.datasheet.in altera corporation 5?1 september 2008 preliminary 5. quartus ii support for hardcopy stratix devices introduction altera ? hardcopy devices provide a comprehensive alternative to asics. hardcopy structured asics offer a complete solution from prototype to high-volume production, and maintain the powerful features and high-performance architecture of their equivalent fpgas with the programmability removed. you can use the quartus ii design software to design hardcopy devices in a manner similar to the traditional asic design flow and you can prototype with altera?s high density stratix, apex 20kc, and apex 20ke fpgas before seamlessly migrating to the corresponding hardcopy device for high-volume production. hardcopy structured asics provide the following key benefits: improves performance, on the average, by 40% over the corresponding -6 speed grade fpga device lowers power consumption, on the average, by 40% over the corresponding fpga preserves the fpga architecture and features and minimizes risk guarantees first-silicon success through a proven, seamless migration process from the fpga to the equivalent hardcopy device offers a quick turnaround of the fpga design to a structured asic device?samples are available in about eight weeks altera?s quartus ii software has built-in support for hardcopy stratix devices. the hardcopy design flow in quartus ii software offers the following advantages: unified design flow from prototype to production performance estimation of the hardcopy stratix device allows you to design systems for maximum throughput easy-to-use and inexpensive design tools from a single vendor an integrated design methodology that enables system-on-a-chip designs h51014-3.4 www.datasheet.in 5?2 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 this section discusses the following areas: how to design hardcopy stratix and hardcopy apex structured asics using the quartus ii software an explanation of what the hardcopy_fpga_prototype devices are and how to target designs to these devices performance and power estimation of hardcopy stratix devices how to generate the hardcopy design database for submitting hardcopy stratix and hardcopy apex designs to the hardcopy design center features beginning with version 4.2, the quartus ii software contains several powerful features that facilitate design of hardcopy stratix and hardcopy apex devices: hardcopy_fpga_prototype devices these are virtual stratix fpga devices with features identical to hardcopy stratix devices. you must use these fpga devices to prototype your designs and verify the functionality in silicon. hardcopy timing optimization wizard using this feature, you can target your design to hardcopy stratix devices, providing an estimate of the design?s performance in a hardcopy stratix device. hardcopy stratix floorplans and timing models the quartus ii software supports post-migration hardcopy stratix device floorplans and timing models and facilitates design optimization for design performance. placement constraints location and logiclock constraints are supported at the hardcopy stratix floorplan level to improve overall performance. improved timing estimation beginning with version 4.2, the quartus ii software determines routing and associated buffer insertion for hardcopy stratix designs, and provides the timing analyzer with more accurate information about the delays than was possible in previous versions of the quartus ii software. the quartus ii archive file automatically receives buffer insertion information, which greatly enhances the timing closure process in the back-end migration of your hardcopy stratix device. www.datasheet.in altera corporation 5?3 september 2008 preliminary hardcopy_fpga_prototype, hardcopy stratix and stratix devices design assistant this feature checks your design for compliance with all hardcopy device design rules and establishes a seamless migration path in the quickest time. hardcopy files wizard this wizard allows you to deliver to altera the design database and all the deliverables required for migration. this feature is used for hardcopy stratix and hardcopy apex devices. f the hardcopy stratix and hardcopy apex powerplay early power estimator is available on the altera website at www.altera.com . hardcopy_fpga _prototype, hardcopy stratix and stratix devices you must use the hardcopy_fpga_prototype virtual devices available in the quartus ii software to target your designs to the actual resources and package options available in the equivalent post-migration hardcopy stratix device. the programming file generated for the hardcopy_fpga_prototype can be used in the corresponding stratix fpga device. the purpose of the hardcopy_fpga_prototype is to guarantee seamless migration to hardcopy by making sure that your design only uses resources in the fpga that can be used in the hardcopy device after migration. you can use the equivalent stratix fpgas to verify the design?s functionality in-system, then generate the design database necessary to migrate to a hardcopy device. this process ensures the seamless migration of the design from a prototyping device to a production device in high volume. it also minimizes risk, assures samples in about eight weeks, and guarantees first-silicon success. 1 hardcopy_fpga_prototype devices are only available for hardcopy stratix devices and are not available for the hardcopy ii or hardcopy apex device families. table 5?1 compares hardcopy_fpga_prototype devices, stratix devices, and hardcopy stratix devices. table 5?1. qualitative comparison of hardcopy_fpga_prototype to stratix and hardcopy stratix devices (part 1 of 2) stratix device hardcopy_fpga_ prototype device hardcopy stratix device fpga virtual fpga structured asic fpga architecture identical to stratix fpga architecture identical to stratix fpga www.datasheet.in 5?4 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 table 5?2 lists the resources available in each of the hardcopy stratix devices. for a given device, the number of available m-ram blocks in hardcopy stratix devices is identical with the corresponding hardcopy_fpga_prototype devices, but may be different from the corresponding stratix devices. maintaining the identical resources between hardcopy_fpga_prototype and hardcopy stratix devices facilitates seamless migration from the fpga to the structured asic device. f for more information about hardcopy stratix devices, refer to the hardcopy stratix device family data sheet section in volume 1 of the hardcopy series handbook. the three devices, stratix fpga, hardcopy_fpga_prototype, and hardcopy device, are distinct devices in the quartus ii software. the hardcopy_fpga_prototype programming files are used in the fpga resources identical to hardcopy stratix device m-ram resources different than stratix fpga in some devices ordered through altera part number cannot be ordered, use the altera stratix fpga part number ordered by altera part number table 5?1. qualitative comparison of hardcopy_fpga_prototype to stratix and hardcopy stratix devices (part 2 of 2) stratix device hardcopy_fpga_ prototype device hardcopy stratix device table 5?2. hardcopy stratix device physical resources device les asic equivalent gates (k) (1) m512 blocks m4k blocks m-ram blocks dsp blocks plls maximum user i/o pins hc1s25f672 25,660 250 224 138 2 10 6 473 hc1s30f780 32,470 325 295 171 2 (2) 12 6 597 hc1s40f780 41,250 410 384 183 2 (2) 14 6 615 HC1S60f1020 57,120 570 574 292 6 18 12 773 hc1s80f1020 79,040 800 767 364 6 (2) 22 12 773 notes to tab le 5 ?2 : (1) combinational and registered logic do not include digital signal processing (dsp) blocks, on-chip ram, or phase-locked loops (plls). (2) the m-ram resources for these hardcopy devices differ from the corresponding stratix fpga. www.datasheet.in altera corporation 5?5 september 2008 preliminary hardcopy design flow stratix fpga for your design. the three devices are tied together with the same netlist, thus a single sram object file ( .sof) can be used to achieve the various goals at each stage. the same sram object file is generated in the hardcopy_fpga_prototype design, and is used to program the stratix fpga device, the same way that it is used to generate the hardcopy stratix device, guaranteeing a seamless migration. f for more information about the sram object file and programming stratix fpga devices, refer to the programming and configuration chapter of the introduction to quartus ii manual . hardcopy design flow figure 5?1 shows a hardcopy design flow diagram. the design steps are explained in detail in the following sections of this chapter. the hardcopy stratix design flow utilizes the hardcopy timing optimization wizard to automate the migration process into a one-step process. the remainder of this section explains the tasks performed by this automated process. f for a detailed description of the hardcopy timing optimization wizard and hardcopy files wizard, refer to ?hardcopy timing optimization wizard summary? and ?generating the hardcopy design database?. www.datasheet.in 5?6 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 figure 5?1. hardcopy stratix and hardcopy apex design flow diagram notes to figure 5?1 : (1) migrate only process: the displayed flow is completed manually. (2) two step process: migration and compilation are done automatically (shaded area). (3) one step process: full hardcopy compilation. the entire process is completed automatically (shaded area). the design flow steps of the one step process the following sections describe each step of the full hardcopy compilation (the one step process), figure 5?1 . compile the design for an fpga this step compiles the design for a hardcopy_fpga_prototype device and gives you the resource utilization and performance of the fpga. stratix apex select stratix hardcopy_fpga_prototype device select apex fpga device supported by hardcopy apex select fpga family mirgrate the compiled project migrate only (1) close the quartus ii fpga project open the quartus ii hardcopy project migrate the compiled project migrate the compiled project two step process (2) one step process (3) compile compile compile placement info for hardcopy run hardcopy files wizard (quartus ii archive file for delivery to altera) compile to hardcopy stratix device (actual hardcopy floorplan) compile to hardcopy stratix device (actual hardcopy floorplan) close the quartus ii fpga project close the quartus ii fpga project open the quartus ii hardcopy project open the quartus ii hardcopy project compile to hardcopy stratix device (actual hardcopy floorplan) start quartus hardcopy flow www.datasheet.in altera corporation 5?7 september 2008 preliminary how to design hardcopy stratix devices migrate the compiled project this step generates the quartus ii project file ( .qpf ) and the other files required for hardcopy implementation. the quartus ii software also assigns the appropriate hardcopy stratix device for the design migration. close the quartus fpga project because you must compile the project for a hardcopy stratix device, you must close the existing project which you have targeted your design to a hardcopy_fpga_prototype device. open the quartus hardcopy project open the quartus ii project that you created in the ?migrate the compiled project? step. the selected device is one of the devices from the hardcopy stratix family that was assigned during that step. compile for hardcopy stratix device compile the design for a hardcopy stratix device. after successful compilation, the timing analysis section of the compilation report shows the performance of the design implemented in the hardcopy device. how to design hardcopy stratix devices this section describes the process for designing for a hardcopy stratix device using the hardcopy_fpga_prototype as your initial selected device. in order to use the hardcopy timing optimization wizard, you must first design with the hardcopy_fpga_prototype in order for the design to migrate to a hardcopy stratix device. to target a design to a hardcopy stratix device in the quartus ii software, follow these steps: 1. if you have not yet done so, create a new project or open an existing project. 2. on the assignments menu, click settings . in the category list, select device . 3. on the device page, in the family list, select stratix . select the desired hardcopy_fpga_prototype device in the available devices list ( figure 5?2 ). www.datasheet.in 5?8 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 figure 5?2. selecting a hardcopy_fpga_prototype device by choosing the hardcopy_fpga_prototype device, all the design information, available resources, package option, and pin assignments are constrained to guarantee a seamless migration of your project to the hardcopy stratix device. the netlist resulting from the hardcopy_fpga_prototype device compilation contains information about the electrical connectivity, resources used, i/o placements, and the unused resources in the fpga device. 4. on the assignments menu, click settings . in the category list, select hardcopy settings and specify the input transition timing to be modeled for both clock and data input pins. these transition times are used in static timing analysis during back-end timing closure of the hardcopy device. 5. add constraints to your hardcopy_fpga_prototype device, and on the processing menu, click start compilation to compile the design. www.datasheet.in altera corporation 5?9 september 2008 preliminary how to design hardcopy stratix devices hardcopy timing optimization wizard after you have successfully compiled your design in the hardcopy_fpga_prototype, you must migrate the design to the hardcopy stratix device to get a performance estimation of the hardcopy stratix device. this migration is required before submitting the design to altera for the hardcopy stratix device implementation. to perform the required migration, on the project menu, point to hardcopy utilities and click hardcopy timing optimization wizard . at this point, you are presented with the following three choices to target the designs to hardcopy stratix devices ( figure 5?3 ). migration only : you can select this option after compiling the hardcopy_fpga_prototype project to migrate the project to a hardcopy stratix project. you can now perform the following tasks manually to target the design to a hardcopy stratix device. refer to ?performance estimation? on page 5?12 for additional information about how to perform these tasks. close the existing project open the migrated hardcopy stratix project compile the hardcopy stratix project for a hardcopy stratix device migration and compilation : you can select this option after compiling the project. this option results in the following actions: migrating the project to a hardcopy stratix project opening the migrated hardcopy stratix project and compiling the project for a hardcopy stratix device full hardcopy compilation : selecting this option results in the following actions: compiling the existing hardcopy_fpga_prototype project migrating the project to a hardcopy stratix project opening the migrated hardcopy stratix project and compiling it for a hardcopy stratix device www.datasheet.in 5?10 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 figure 5?3. hardcopy timing optimization wizard options the main benefit of the hardcopy timing wizard?s three options is flexibility of the conversion process automation. the first time you migrate your hardcopy_fpga_prototype project to a hardcopy stratix device, you may want to use migration only, and then work on the hardcopy stratix project in the quartus ii software. as your prototype fpga project and hardcopy stratix project constraints stabilize and you have fewer changes, the full hardcopy compilation is ideal for one-click compiling of your hardcopy_fpga_prototype and hardcopy stratix projects. www.datasheet.in altera corporation 5?11 september 2008 preliminary how to design hardcopy stratix devices after selecting the wizard you want to run, the ?hardcopy timing optimization wizard: summary? page shows you details about the settings you made in the wizard, as shown in ( figure 5?4 ). figure 5?4. hardcopy timing optimization wizard summary page when either of the second two options in figure 5?4 are selected ( migration and compilation or full hardcopy compilation ), designs are targeted to hardcopy stratix devices and optimized using the hardcopy stratix placement and timing analysis to estimate performance. for details on the performance optimization and estimation steps, refer to ?performance estimation? on page 5?12 . if the performance requirement is not met, you can modify your rtl source, optimize the fpga design, and estimate timing until you reach timing closure. tcl support for hardcopy migration to complement the gui features for hardcopy migration, the quartus ii software provides the following command-line executables (which provide the tool command language (tcl) shell to run the --flow tc l command) to migrate the hardcopy_fpga_prototype project to hardcopy stratix devices: quartus_sh --flow migrate_to_hardcopy < project_name > [ -c < revision >] r this command migrates the project compiled for the hardcopy_fpga_prototype device to a hardcopy stratix device. www.datasheet.in 5?12 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 quartus_sh --flow hardcopy_full_compile < project_name > [ -c < revision > ] r this command performs the following tasks: compiles the exsisting project for a hardcopy_fpga_prototype device. migrates the project to a hardcopy stratix project. opens the migrated hardcopy stratix project and compiles it for a hardcopy stratix device. design optimization and performance estimation the hardcopy timing optimization wizard creates the hardcopy stratix project in the quartus ii software, where you can perform design optimization and performance estimation of your hardcopy stratix device. design optimization beginning with version 4.2, the quartus ii software supports hardcopy stratix design optimization by providing floorplans for placement optimization and hardcopy stratix timing models. these features allows you to refine placement of logic array blocks (lab) and optimize the hardcopy design further than the fpga performance. customized routing and buffer insertion done in the quartus ii software are then used to estimate the design?s performance in the migrated device. the hardcopy device floorplan, routing, and timing estimates in the quartus ii software reflect the actual placement of the design in the hardcopy stratix device, and can be used to see the available resources, and the location of the resources in the actual device. performance estimation figure 5?5 illustrates the design flow for estimating performance and optimizing your design. you can target your designs to hardcopy_fpga_prototype devices, migrate the design to the hardcopy stratix device, and get placement optimization and timing estimation of your hardcopy stratix device. in the event that the required performance is not met, you can: work to improve lab placement in the hardcopy stratix project. or www.datasheet.in altera corporation 5?13 september 2008 preliminary design optimization and performance estimation go back to the hardcopy_fpga_prototype project and optimize that design, modify your rtl source code, repeat the migration to the hardcopy stratix device, and perform the optimization and timing estimation steps. 1 on average, hardcopy stratix devices are 40% faster than the equivalent -6 speed grade stratix fpga device. these performance numbers are highly design dependent, and you must obtain final performance numbers from altera. figure 5?5. obtaining a hardcopy performance estimation to perform timing analysis for a hardcopy stratix device, follow these steps: 1. open an existing project compiled for a hardcopy_fpga_protoype device. 2. on the project menu, point to hardcopy utilities and click hardcopy timing optimization wizard . 3. select a destination directory for the migrated project and complete the hardcopy timing optimization wizard process. on completion of the hardcopy timing optimization wizard, the destination directory created contains the quartus ii project file, and all files required for hardcopy stratix implementation. at this stage, the design is copied from the hardcopy_fpga_prototype project directory to a new directory to perform the timing analysis. this two-project directory structure enables you to move back and forth between the hardcopy_fpga_prototype design database and the hardcopy stratix design database. the quartus ii software creates the < project name > _hardcopy_optimization directory. you do not have to select the hardcopy stratix device while performing performance estimation. when you run the hardcopy timing optimization wizard, the quartus ii software selects the no ye s timing met? proven netlist & new timing & placement constraint proven netlist, pin assignments, & timing constraints stratix fpga hardcopy placement & timing analysis hardcopy stratix www.datasheet.in 5?14 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 hardcopy stratix device corresponding to the specified hardcopy_fpga_prototype fpga. thus, the information necessary for the hardcopy stratix device is available from the earlier hardcopy_fpga_prototype device selection. all constraints related to the design are also transferred to the new project directory. you can modify these constraints, if necessary, in your optimized design environment to achieve the necessary timing closure. however, if the design is optimized at the hardcopy_fpga_prototype device level by modifying the rtl code or the device constraints, you must migrate the project with the hardcopy timing optimization wizard. c if an existing project directory is selected when the hardcopy timing optimization wizard is run, the existing information is overwritten with the new compile results. www.datasheet.in altera corporation 5?15 september 2008 preliminary design optimization and performance estimation the project directory is the directory that you chose for the migrated project. a snapshot of the files inside the 5?16 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 1 performance estimation is not supported for hardcopy apex devices in the quartus ii software. your design can be optimized by modifying the rtl code or the fpga design and the constraints. you should contact altera to discuss any desired performance improvements with hardcopy apex devices. buffer insertion beginning with version 4.2, the quartus ii software provides improved hardcopy stratix device timing closure and estimation, to more accurately reflect the results expected after back-end migration. the quartus ii software performs the necessary buffer insertion in your hardcopy stratix device during the fitter process, and stores the location of these buffers and necessary routing information in the quartus ii archive file. this buffer insertion improves the estimation of the quartus ii timing analyzer for the hardcopy stratix device. placement constraints beginning with version 4.2, the quartus ii software supports placement constraints and logiclock regions for hardcopy stratix devices. figure 5?6 shows an iterative process to modify the placement constraints until the best placement for the hardcopy stratix device is achieved. www.datasheet.in altera corporation 5?17 september 2008 preliminary location constraints figure 5?6. placement constraints flow for hardcopy stratix devices location constraints this section provides information about hardcopy stratix logic location constraints. lab assignments logic placement in hardcopy stratix is limited to lab placement and optimization of the interconnecting signals between them. in a stratix fpga, individual logic elements (le) are placed by the quartus ii fitter into labs. the hardcopy stratix migration process requires that lab contents cannot change after the timing optimization wizard task is done. therefore, you can only make lab-level placement optimization and location assignments after migrating the hardcopy_fpga_prototype project to the hardcopy stratix device. migrate to hardcopy stratix device using the hardcopy timing optimization wizard add/update placement constraints add/update logiclock constraints compile for hardcopy stratix device ye s no compile the design for hardcopy_fpga_prototype generate hardcopy files performance met? www.datasheet.in 5?18 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 the quartus ii software supports these lab location constraints for hardcopy stratix devices. the entire contents of a lab is moved to an empty lab when using lab location assignments. if you want to move the logic contents of lab a to lab b, the entire contents of lab a are moved to an empty lab b. for example, the logic contents of lab_x33_y65 can be moved to an empty lab at lab_x43_y56 but individual logic cell lc_x33_y65_n1 can not be moved by itself in the hardcopy stratix timing closure floorplan. logiclock assignments the logiclock feature of the quartus ii software provides a block-based design approach. using this technique you can partition your design and create each block of logic independently, optimize placement and area, and integrate all blocks into the top level design. f to learn more about this methodology, refer to the quartus ii analyzing and optimizing design floorplan chapter in volume 2 of the quartus ii handbook . logiclock constraints are supported when you migrate the project from a hardcopy_fpga_prototype project to a hardcopy stratix project. if the logiclock region was specified as ? size=fixed ? and ? location=locked ? in the hardcopy_fpga_prototype project, it is converted to have ? size=auto ? and ? location=floating ? as shown in the following logiclock examples. this modification is necessary because the floorplan of a hardcopy stratix device is different from that of the stratix device, and the assigned coordinates in the hardcopy_fpga_prototype do not match the hardcopy stratix floorplan. if this modification did not occur, logiclock assignments would lead to incorrect placement in the quartus ii fitter. making the regions auto-size and floating, maintains your logiclock assignments, allowing you to easily adjust the logiclock regions as required and lock their locations again after hardcopy stratix placement. the following are two examples of logiclock assignments. logiclock region definition in the hardcopy_fpga_prototype quartus ii settings file set_global_assignment -name ll_height 15 -entity risc8 -section_id test set_global_assignment -name ll_width 15 -entity risc8 -section_id test set_global_assignment -name ll_state locked -entity risc8 -section_id test set_global_assignment -name ll_auto_size off -entity risc8 -section_id test www.datasheet.in altera corporation 5?19 september 2008 preliminary checking designs for hardcopy design guidelines logiclock region definition in the migrated hardcopy stratix quartus ii settings file set_global_assignment -name ll_height 15 -entity risc8 -section_id test set_global_assignment -name ll_width 15 -entity risc8 -section_id test set_global_assignment -name ll_state floating -entity risc8 -section_id test set_global_assignment -name ll_auto_size on -entity risc8 -section_id test checking designs for hardcopy design guidelines when you develop a design with hardcopy migration in mind, you must follow altera-recommended design practices that ensure a straightforward migration process or the design will not be able to be implemented in a hardcopy device. prior to starting migration of the design to a hardcopy device, you must review the design and identify and address all the design issues. any design issues that have not been addressed can jeopardize silicon success. altera recommended hdl coding guidelines designing for altera pld, fpga, and hardcopy structured asic devices requires certain specific design guidelines and hardware description language (hdl) coding style recommendations be followed. f for more information about design recommendations and hdl coding styles, refer to the design guidelines section in volume 1 of the quartus ii handbook . design assistant the quartus ii software includes the design assistant feature to check your design against the hardcopy design guidelines. some of the design rule checks performed by the design assistant include the following rules: design should not contain combinational loops design should not contain delay chains design should not contain latches to use the design assistant, you must run analysis and synthesis on the design in the quartus ii software. altera recommends that you run the design assistant to check for compliance with the hardcopy design guidelines early in the design process and after every compilation. www.datasheet.in 5?20 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 design assistant settings you must select the design rules in the design assistant page prior to running the design. on the assignments menu, click settings . in the settings dialog box, in the category list, select design assistant and turn on run design assistant during compilation . altera recommends enabling this feature to run the design assistant automatically during compilation of your design. running design assistant to run design assistant independently of other quartus ii features, on the processing menu, point to start and click start design assistant . the design assistant automatically runs in the background of the quartus ii software when the hardcopy timing optimization wizard is launched, and does not display the design assistant results immediately to the display. the design is checked before the quartus ii software migrates the design and creates a new project directory for performing timing analysis. also, the design assistant runs automatically whenever you generate the hardcopy design database with the hardcopy files wizard. the design assistant report generated is used by the altera hardcopy design center to review your design. reports and summary the results of running the design assistant on your design are available in the design assistant results section of the compilation report. the design assistant also generates the summary report in the < project name >\ hardcopy subdirectory of the project directory. this report file is titled < project name >_ violations.datasheet . reports include the settings, run summary, results summary, and details of the results and messages. the design assistant report indicates the rule name, severity of the violation, and the circuit path where any violation occurred. f to learn about the design rules and standard design practices to comply with hardcopy design rules, refer to the quartus ii help and the hardcopy series design guidelines chapter in volume 1 of the hardcopy series handbook. www.datasheet.in altera corporation 5?21 september 2008 preliminary generating the hardcopy design database generating the hardcopy design database you can use the hardcopy files wizard to generate the complete set of deliverables required for migrating the design to a hardcopy device in a single click. the hardcopy files wizard asks questions related to the design and archives your design, settings, results, and database files for delivery to altera. your responses to the design details are stored in 5?22 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 figure 5?4 shows the archive directory structure and files collected by the hardcopy files wizard. after creating the migration database with the hardcopy timing optimization wizard, you must compile the design before generating the project archive. you will receive an error if you create the archive before compiling the design. table 5?4. hardcopy stratix design files collected by the hardcopy files wizard altera corporation 5?23 september 2008 preliminary static timing analysis static timing analysis in addition to performing timing analysis, the quartus ii software also provides all of the requisite netlists and tcl scripts to perform static timing analysis (sta) using the synopsys sta tool, primetime. the following files, necessary for timing analysis with the primetime tool, are generated by the hardcopy files wizard: < project name > _hcpy.vo ?verilog hdl output format < project name > _hpcy_v.sdo ?standard delay format output file < project name > _pt_hcpy_v.tcl ?tcl script these files are available in the < project name > \hardcopy directory. primetime libraries for the hardcopy stratix and stratix devices are included with the quartus ii software. 1 use the hardcopy stratix libraries for primetime to perform sta during timing analysis of designs targeted to hardcopy_fpga_prototype device. f for more information about static timing analysis, refer to the classic timing analyzer and the synopsys primetime support chapters in volume 3 of the quartus ii handbook . early power estimation you can use powerplay early power estimation to estimate the amount of power your hardcopy stratix or hardcopy apex device will consume. this tool is available on the altera website. using the early power estimator requires some knowledge of your design resources and specifications, including: target device and package clock networks used in the design resource usage for les, dsp blocks, pll, and ram blocks high speed differential interfaces (hsdi), general i/o power consumption requirements, and pin counts environmental and thermal conditions hardcopy stratix early power estimation the powerplay early power estimator provides an initial estimate of i cc for any hardcopy stratix device based on typical conditions. this calculation saves significant time and effort in gaining a quick understanding of the power requirements for the device. no stimulus vectors are necessary for power estimation, which is established by the clock frequency and toggle rate in each clock domain. www.datasheet.in 5?24 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 this calculation should only be used as an estimation of power, not as a specification. the actual i cc should be verified during operation because this estimate is sensitive to the actual logic in the device and the environmental operating conditions. f for more information about simulation-based power estimation, refer to the power estimation and analysis section in volume 3 of the quartus ii handbook. 1 on average, hardcopy stratix devices are expected to consume 40% less power than the equivalent fpga. hardcopy apex early power estimation the powerplay early power estimator can be run from the altera website in the device support section ( http://www.altera.com/support/devices/dvs-index.html ). you cannot open this feature in the quartus ii software. with the hardcopy apex powerplay early power estimator, you can estimate the power consumed by hardcopy apex devices and design systems with the appropriate power budget. refer to the web page for instructions on using the hardcopy apex powerplay early power estimator. 1 hardcopy apex devices are generally expected to consume about 40% less power than the equivalent apex 20ke or apex 20kc fpga devices. tcl support for hardcopy stratix the quartus ii software also supports the hardcopy stratix design flow at the command prompt using tcl scripts. f for details on quartus ii support for tcl scripting, refer to the tcl s cr i p t i n g chapter in volume 2 of the quartus ii handbook . www.datasheet.in altera corporation 5?25 september 2008 preliminary targeting designs to hardcopy apex devices targeting designs to hardcopy apex devices beginning with version 4.2, the quartus ii software supports targeting designs to hardcopy apex device families. after compiling your design for one of the apex 20kc or apex 20ke fpga devices supported by a hardcopy apex device, run the hardcopy files wizard to generate the necessary set of files for hardcopy migration. the hardcopy apex device requires a different set of design files for migration than hardcopy stratix. table 5?5 shows the files collected for hardcopy apex by the hardcopy files wizard. refer to ?generating the hardcopy design database? on page 5?21 for information about generating the complete set of deliverables required for migrating the design to a hardcopy apex device. after you have successfully run the hardcopy files wizard, you can submit your design archive to altera to implement your design in a hardcopy device. you should contact altera for more information about this process. conclusion the methodology for designing hardcopy stratix devices using the quartus ii software is the same as that for designing the stratix fpga equivalent. you can use the familiar quartus ii software tools and design flow, target designs to hardcopy stratix devices, optimize designs for higher performance and lower power consumption than the stratix fpgas, and deliver the design database for migration to a hardcopy stratix device. compatible apex fpga designs can migrate to hardcopy apex after compilation using the hardcopy files wizard to archive the design files. submit the files to the hardcopy design center to complete the back-end migration. table 5?5. hardcopy apex files collected by the hardcopy files wizard 5?26 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 related documents for more information, refer to the following documentation: the hardcopy series design guidelines chapter in volume 1 of the hardcopy series handbook. the hardcopy series back-end timing closure chapter in volume 1 of the hardcopy series handbook. document revision history table 5?6 shows the revision history for this chapter. table 5?6. document revision history date and document version changes made summary of changes september 2008 v3.4 updated chapter number and metadata. ? june 2007 v3.3 updated with the current quartus ii software version 7.1 information. ? december 2006 v3.2 updated revision history. ? march 2006 formerly chapter 20; no content change. ? october 2005 v3.1 updated for technical contents for quartus ii 5.1 release minor edits minor edits. may 2005 v3.0 added powerplay early power estimator information. ? january 2005 v2.0 this revision was previously the quartus ? ii support for hardcopy devices chapter in the quartus ii development software handbook, v4.1. ? august 2003 v1.1 overall edit; added tcl script appendix. ? june 2003 v1.0 initial release of chapter 20, quartus ii support for hardcopy stratix devices. ? www.datasheet.in altera corporation 6?1 september 2008 6. design guidelines for hardcopy stratix performance improvement introduction advanced design techniques using altera ? hardcopy ? stratix ? devices can yield tremendous performance improvements over the design implemented in a stratix fpga device. after you verify your stratix fpga design in system operation and are ready to migrate to a hardcopy stratix device, additional device performance is possible through the migration. this chapter focuses on quartus ? ii software advanced design techniques that apply to both stratix fpga devices and hardcopy stratix devices. use these techniques to increase your maximum clock frequency, improve input and output pin timing, and improve timing closure in hardcopy stratix designs. 1 every design is different. the techniques described in this chapter may not apply to every design, and may not yield the same level of improvement. this document discusses the following topics: planning stratix fpga design for hardcopy stratix design conversion using logiclock? regions in hardcopy stratix designs using design space explorer (dse) on hardcopy stratix designs design performance improvement example background information to understand the quartus ii software and device architecture, and to use the advanced design techniques described in this chapter, altera recommends reading the hardcopy series handbook and the following chapters in the quartus ii software handbook : design recommendations for altera devices and the quartus ii design assistant design optimization for altera devices design space explorer analyzing and optimizing the design floorplan netlist optimizations and physical synthesis h51027-1.4 www.datasheet.in 6?2 altera corporation september 2008 planning stratix fpga design for hardcopy stratix design conversion planning stratix fpga design for hardcopy stratix design conversion in order to achieve greater performance improvement in your hardcopy stratix device, additional quartus ii software constraints and placement techniques in the hardcopy_fpga_prototype design project may be necessary. this does not mean changing the source hardware description language (hdl) code or functionality, but providing additional constraints in the quartus ii software that specifically impact hardcopy stratix timing optimization. planning ahead for migration to the hardcopy design, while still modifying the hardcopy_fpga_prototype design, can improve design performance results. you must anticipate how portions of your fpga design are placed and connected in the hardcopy device floorplan. the hardcopy device floorplan is smaller than the fpga device floorplan, allowing use of the customized metal routing in hardcopy stratix devices. partitioning your design partitioning your design into functional blocks is essential in multi-million gate designs. with a hardcopy stratix device, you can implement approximately one million asic gates of logic. therefore, altera recommends hierarchical-design partitioning based on system functions. when using a hierarchical- or incremental-design methodology, you must consider how your design is partitioned to achieve good results. altera recommends the following practices for partitioning designs as documented in the design recommendations for altera devices chapter in volume 1 of the quartus ii development software handbook : partition your design at functional boundaries. minimize the i/o connections between different partitions. register all inputs and outputs of each block. this makes logic synchronous and avoids glitches and any delay penalty on signals that cross between partitions. registering i/o pins typically eliminates the need to specify timing requirements for signals that connect between different blocks. do not use glue logic or connection logic between hierarchical blocks. when you preserve hierarchy boundaries, glue logic is not merged with hierarchical blocks. your synthesis software may optimize glue logic separately, which can degrade synthesis results and is not efficient when used with the logiclock design methodology. logic is not synthesized or optimized across partition boundaries. any constant values (for example, signals set to gnd), are not propagated across partitions. www.datasheet.in altera corporation 6?3 september 2008 design guidelines for hardcopy stratix performance improvement do not use tri-state signals or bidirectional ports on hierarchical boundaries. if you use tri-state boundaries in a lower-level block, synthesis pushes the tri-state signals through the hierarchy to the top-level. this takes advantage of the tri-state drivers on the output pins of the altera device. since this requires optimizing through hierarchies, lower-level boundary tri-state signals are not supported with a block-level design methodology. limit clocks to one per block. partitioning your design into clock domains makes synthesis and timing analysis easier. place state machines in separate blocks to speed optimization and provide greater encoding control. separate timing-critical functions from non-timing-critical functions. limit the critical timing path to one hierarchical block. group the logic from several design blocks to ensure the critical path resides in one block. these guidelines apply to all altera device architectures including hardcopy stratix devices. partitioning functional boundaries to have all outputs immediately registered is crucial to using logiclock regions effectively in hardcopy devices. with registered outputs, you allow the signals to leave a function block at the start of the clock period. this gives the signals more set-up time to reach their endpoints in the clock period. in large designs that are partitioned into multiple function blocks, the block-to-block interconnects are often the limiting factor for f max performance. registered outputs give the quartus ii fitter the optimal place-and-route flexibility for interconnects between major function blocks. physical synthesis optimization all physical synthesis settings in the quartus ii software can be used in the hardcopy_fpga_prototype design. these settings are found in the physical synthesis optimizations section of the fitter settings dialog box (assignments menu) and include the following settings: physical synthesis for combinational logic register duplication register retiming these settings can improve fpga performance while developing the hardcopy_fpga_prototype. all modifications are passed along into the hardcopy stratix project when you run the hardcopy timing optimization wizard. after running the hardcopy timing optimization wizard and subsequently opening the hardcopy project in the quartus ii software, these physical synthesis optimizations are disabled. no further modifications to the netlist are made. www.datasheet.in 6?4 altera corporation september 2008 using logiclock regions in hardcopy stratix designs altera recommends physical synthesis optimizations for the hardcopy_fpga_prototype. the work done in the prototype enhances performance in the hardcopy stratix device after migration. duplicating combinational logic and registers can increase area utilization, which limits placement flexibility when designs exceed 95% logic element (le) utilization. however, duplicating combinational logic and registers can help with performance by allowing critical paths to be duplicated when their endpoints must reach different areas of the device floorplan. f for more information on netlist and design optimization, refer to area optimization and timing closure in volume 2 of the quartus ii development software handbook . using logiclock regions in hardcopy stratix designs create logiclock regions in the hardcopy_fpga_prototype project and migrate the regions into the hardcopy stratix optimization project using the quartus ii software. logiclock regions can provide significant benefits in design performance by carefully isolating critical blocks of logic, including: megacore ? ip functions i/o interfaces reset or other critical logic feeding global clock lines partitioned function blocks you must compile your design initially without logiclock regions present and review the timing analysis reports to determine if additional constraints or logiclock regions are necessary. this process allows you to determine which function blocks or data paths require logiclock regions. create logiclock regions in the hardcopy_fpga_prototype design project in the quartus ii software. this transfers the logiclock regions to the hardcopy design project after the hardcopy timing optimization wizard is run. although the quartus ii software transfers the contents of the logiclock region, the area, location, and soft boundary settings revert to their default settings in the hardcopy project immediately after the hardcopy timing optimization wizard is run. if you are using logiclock regions, altera recommends you use the migration only setting in the hardcopy timing optimization wizard to create the hardcopy design project. you should not compile your design automatically using the full compilation or migrate and compile options in the wizard. open the hardcopy design project and verify that the logiclock region properties meet your desired settings before compiling the hardcopy optimization project. logiclock soft regions are www.datasheet.in altera corporation 6?5 september 2008 design guidelines for hardcopy stratix performance improvement turned on by default in the hardcopy stratix design. while this does allow the fitter to place all logic in your design with fewer restrictions, it is not optimal for performance improvement in the hardcopy stratix design. recommended logiclock settings for hardcopy stratix designs altera recommends the following logiclock region settings for the hardcopy_fpga_prototype: tu r n o n reserve unused logic turn off soft region select either auto or fixed as the size (design-dependent) select either floating or locked as the location (design-dependent) when using the reserve unused logic setting in a design with high resource utilization (> 95% le utilization), and a large number of logiclock regions, the design may not fit in the device. turning off reserve unused logic in less critical logiclock regions can help fitter placement. the les allowed to float in placement and be packed into unused les of logiclock regions may not be placed optimally after migration to the hardcopy stratix device since they are merged with other logiclock regions. after running the hardcopy timing optimization wizard, the logiclock region properties are reset to their default conditions. this allows a successful and immediate placement of your design in the quartus ii software. you can further refine the logiclock region properties for additional benefits. altera recommends using the following properties for logiclock regions in the hardcopy design project: turn off soft region select either auto or fixed as the size after you are satisfied with the placement and timing result of a logiclock region in a successful hardcopy stratix compilation select either floating or locked as the location after you are satisfied with the placement and timing results reserve unused logic is not applicable in the hardcopy stratix device placement because logic array block (lab) contents can not be changed after the hardcopy timing optimization wizard is run an example of a well partitioned design using logiclock regions effectively for some portions of the design is shown in figure 6?1 . only the most critical logic functions required are placed in logiclock regions in order to achieve the desired performance in the hardcopy stratix www.datasheet.in 6?6 altera corporation september 2008 using design space explorer for hardcopy stratix designs device. the dark blue rectangles shown in figure 6?1 are the user-assigned logiclock regions that have fixed locations. in this example, the design needed to be constrained by logiclock regions first inside the hardcopy_fpga_prototype with reserve unused logic turned off in properties in logiclock regions. this selection allows the quartus ii software to isolate and compact the logic of these blocks in the hardcopy_fpga_prototype such that the placement is tightly controlled in the hardcopy stratix device. figure 6?1. a well partitioned design in the example shown in figure 6?1 , once suitable locations were identified for logiclock regions, the logiclock region properties were changed from floating to locked. the quartus ii software can then reproduce their placement in subsequent compilations, while focusing attention on fixing other portions of the design. using design space explorer for hardcopy stratix designs the dse feature in the quartus ii software allows you to evaluate various compilation settings to achieve the best results for your fpga designs. dse can also be used in the hardcopy stratix project after running the hardcopy timing optimization wizard. only some of the dse settings affect hardcopy stratix designs because hdl synthesis and physical optimization have been completed on the fpga. no logic restructuring can occur after using the hardcopy timing optimization wizard. when you compile your design, the placement of labs is optimized in the hardcopy stratix device. to access the dse gui www.datasheet.in altera corporation 6?7 september 2008 design guidelines for hardcopy stratix performance improvement in your open project in the quartus ii software, select launch design space explorer (tools menu). an example of the dse gui and dse settings window for the hardcopy stratix device is shown in figure 6?2 . figure 6?2. dse settings window in the dse gui recommended dse settings for hardcopy stratix designs the hardcopy stratix design does not require all advanced settings or effort-level settings in dse. altera recommends using the following settings in dse for hardcopy stratix designs: in the settings tab ( figure 6?2 ), make the following selections: under project settings , enter several seed numbers in the seeds box. each seed number requires one full compile of the hardcopy stratix project. under project settings , select allow logiclock region restructuring. under exploration settings , select search for best performance, and select low (seed sweep) from the effort level menu. tu r n o n archive all compilations (options menu). after running dse with the seed sweep setting, view the results and identify which seed settings produced the best compilation results. use the archive of the identified seed, or merge the compilation settings and seed number from the dse archived project into your primary hardcopy stratix project. www.datasheet.in 6?8 altera corporation september 2008 performance improvement example performance improvement example with the design used for the performance improvement example in this section, the designer was seeking performance improvement on an hc1s30f780 design for an intellectual property (ip) core consisting of approximately 5200 les, 75,000 bits of memory, and two digital signal processing (dsp) multiplier accumulators (macs). the final application needed to fit in a reserved portion of the hc1s30 device floorplan, so the entire block of ip was initially bounded in a single logiclock region. the ip block was evaluated as a stand-alone block. initial design example settings the default settings in the quartus ii software version 4.2 were used, with the following initial constraints added: the device was set to the target stratix fpga device which is the prototype for the hc1s30f780 device: set_global_assignment -name device ep1s30f780c6_hardcopy_fpga_prototype a logiclock region was created for the block to bound it in the reserved region. the logiclock region properties were set to auto size and floating location , and reserve unused logic was turned on: set_global_assignment -name ll_state floating set_global_assignment -name ll_auto_size on set_global_assignment -name ll_reserved off set_global_assignment -name ll_soft off virtual i/o pins were used for the ports of the core since this core does not interface to pins in the parent design, and the i/o pins were placed outside the logiclock region and are represented as registers in les. the initial compilation results yielded 65.30-mhz f max in the fpga. the block was constrained through virtual i/o pins and a logiclock region to keep the logic from spreading throughout the floorplan. www.datasheet.in altera corporation 6?9 september 2008 design guidelines for hardcopy stratix performance improvement the initial compile-relevant statistics for this example are provided in table 6?1 . the design project was migrated to the hardcopy device using the hardcopy timing optimization wizard and was compiled. the default settings of the logiclock region in a hardcopy stratix project in the quartus ii software have the soft region option turned on. with this setting, the hardcopy stratix compilation yields an f max of 66.48 mhz, mainly due to the fitter placement being scattered in an open design ( figure 6?3 ). because the soft region is set to on, the logiclock region is not bounded. this is not an optimal placement in the hardcopy stratix design and is not the best possible performance. table 6?1. initial compilation statistics result type results f max 65.30 mhz total logic elements (les) 5,187/32,470 (15%) total labs 564/3,247 (17%) m512 blocks 20/295 (6%) m4k blocks 16/171 (9%) m-ram blocks 0/2 (0%) total memory bits 74,752/2,137,536 (3%) total ram block bits 85,248/2,137,536 (3%) dsp block 9-bit elements 2/96 (2%) www.datasheet.in 6?10 altera corporation september 2008 performance improvement example figure 6?3. hardcopy stratix device floorplan with soft region on to keep the logiclock region contents bounded in the final placement in the hardcopy stratix device floorplan, turn off the soft region option. after turning off the soft region option and compiling the hardcopy stratix design, the result is an f max of 88.14 mhz?a gain of 33% over the stratix fpga device performance. the bounded placement in the logiclock region helps to achieve performance improvement in well-partitioned design blocks by taking advantage of the smaller die size and custom metal routing interconnect of the hardcopy stratix device. the floorplan of the bounded logiclock region is visible in figure 6?4 . in this figure, you can see the difference in disabling the soft region setting in the hardcopy stratix design. www.datasheet.in altera corporation 6?11 september 2008 design guidelines for hardcopy stratix performance improvement figure 6?4. hardcopy stratix device floorplan with soft region off using analysis and synthesis settings for performance improvement after establishing the baseline for improvement for this design of 65.30 mhz fpga/88.14 mhz hardcopy, you can gain additional performance improvement in the stratix fpga and hardcopy stratix devices using the available features in the quartus ii software. changing the analysis & synthesis effort from balanced to speed yields additional benefit in performance, but at the cost of additional le resources. the tcl command for this assignment is as follows: set_global_assignment -name stratix_optimization_technique speed www.datasheet.in 6?12 altera corporation september 2008 performance improvement example the relevant compilation results of the fpga are provided in table 6?2 . increasing the le resources by 6% only yielded an additional 3 mhz in performance in the fpga, without using additional settings. however, after migrating this design to the hardcopy stratix design and compiling it, the performance did not improve over the previous hardcopy stratix design compile, and was slightly worse in performance at 87.34 mhz. this shows that the quartus ii software synthesis was very effective with the synthesis effort level set to balanced , and there was only marginal improvement in the fpga when this option was set to speed . the next settings activated in this example were the synthesis netlist optimizations shown below in tcl format for wysiwyg synthesis remapping and gate-level retiming after synthesis mapping: set_global_assignment -name adv_netlist_opt_synth_wysiwyg_remap on set_global_assignment -name adv_netlist_opt_synth_gate_retime on table 6?2. relevant compile results result type results f max 68.88 mhz total logic elements 5,508/32,470 (16%) total labs 598/3,247 (18%) m512 blocks 20/295 (6%) m4k blocks 16/171 (9%) m-ram blocks 0/2 (0%) total memory bits 74,752/2,137,536 (3%) total ram block bits 85,248/2,137,536 (3%) dsp block 9-bit elements 2/96 (2%) www.datasheet.in altera corporation 6?13 september 2008 design guidelines for hardcopy stratix performance improvement making these settings in the fpga while leaving analysis & synthesis effort set to speed yielded some additional improvement in the fpga as shown in table 6?3 . the wysiwyg resynthesis added a minimal increase in les over the speed setting, and the design performance improved by 2 mhz in the fpga. using the hardcopy timing optimization wizard to migrate the design to hardcopy and subsequently compiling the hardcopy stratix design, we find that performance is not improved beyond previous compiles, with an f max of 86.58 mhz. the quartus ii software automatically optimizes state machines and restructures multiplexers when these settings are set to auto in the analysis & synthesis settings. changing these options from auto usually does not yield performance improvement. for example, changing the multiplexer restructuring and state machine processing settings from both set to auto , to on and one-hot , respectively, actually hurt performance, not allowing the quartus ii software to determine the optimization on a case-by-case basis. with these settings, the fpga compiled to an f max of 65.99 mhz, and the hardcopy stratix design only performed at 83.77 mhz. for this design example, it is better to leave these settings to auto as seen in the tcl assignments in the ?using fitter assignments and physical synthesis optimizations for performance improvement? section, and allow the quartus ii software to determine when to use these features. using fitter assignments and physical synthesis optimizations for performance improvement after exploring the analysis & synthesis optimization settings in the quartus ii software, you can use the fitter settings and physical synthesis optimization features to gain further performance improvement in your stratix fpga and hardcopy stratix devices. in this design example, multiplexer and state machine restructuring settings have been set to auto , and the synthesis optimization technique is set table 6?3. results of analysis & synthesis effort set to speed result type results f max 70.28 mhz total logic elements 5,515/32,470 (16%) total labs 597/3,247 (18%) www.datasheet.in 6?14 altera corporation september 2008 performance improvement example for speed . the fitter effort is set to standard fit (highest effort) . the next features enabled are the physical synthesis optimizations as seen in the tcl assignments below and in figure 6?5 : set_global_assignment -name physical_synthesis_combo_logic on set_global_assignment -name physical_synthesis_register_duplication on set_global_assignment -name physical_synthesis_register_retiming on set_global_assignment -name physical_synthesis_effort extra figure 6?5. physical synthesis optimization settings the compiled design shows a performance increase in the fpga, running at an f max of 74.34 mhz, requiring additional le resources as a result of the physical synthesis and logic duplication. in this example, you can see how performance can be increased in the stratix fpga device at the expense of additional le resources, as this design?s le resources grew almost 12% over the beginning compilation. the compiled fpga design?s statistics are provided in table 6?4 . table 6?4. compiled fpga design statistics result type results f max 74.34 mhz total logic elements 5,781/32,470 (17%) total labs 610/3,247 (18%) www.datasheet.in altera corporation 6?15 september 2008 design guidelines for hardcopy stratix performance improvement running the hardcopy timing optimization wizard on this design and compiling the hardcopy stratix project yields an f max of 92.01 mhz, a 24% improvement over the fpga timing. design space explorer the available fitter settings produce an additional performance improvement. the dse feature is used on the stratix fpga device to run through the various seeds in the design and select the best seed point to use for future compiles. this can often yield additional performance benefits as the quartus ii software further refines placement of the les and performs clustering of associated logic together. for this design example, dse was run with high effort (physical synthesis) and multiple placement seeds. table 6?5 shows the dse results. the base compile matches the fifth compile in the dse variations, showing that the work already done on the design before dse was optimal. the fpga project was optimized before running dse. table 6?5. dse results compile point clock period: clk logic cells base (best) 13.451 ns (74.34 mhz) 5,781 1 13.954 ns 5,703 2 13.712 ns 6,447 3 14.615 ns 5,777 4 13.911 ns 5,742 5 13.451 ns 5,781 6 14.838 ns 5,407 7 14.177 ns 5,751 8 14.479 ns 5,827 9 14.863 ns 5,596 10 14.662 ns 5,605 11 14.250 ns 5,710 12 14.016 ns 5,708 13 13.840 ns 5,802 14 13.681 ns 5,788 15 14.829 ns 5,644 www.datasheet.in 6?16 altera corporation september 2008 performance improvement example additional correlation is seen inside the < project > .dse.rpt file, showing the summary of assignments used for each compile inside the quartus ii software. the base compile settings and the fifth compile settings show good correlation, as shown in table 6?6 . the mux_restructure setting did not have any effect on the design performance. this may be due to an already efficient hdl coding for multiplexer structures, requiring no optimization. the information presented in table 6?6 con firms th at the fpga prototype device has been optimized as much as possible without manual floorplan adjustments. design space explorer for hardcopy stratix devices migrating this compiled design to the hardcopy stratix project and compiling the hardcopy stratix design optimization, results in a design performance of 92.01 mhz. the next task is to run dse on the hardcopy stratix project using low effort (seed sweep) in the exploration settings , and entering a range of seed numbers with which to compile the project. table 6?6. base compile and fifth compile correlation setting new value base value physical_synthesis_register_retiming on on seed 1 1 state_machine_processing auto auto mux_restructure off auto physical_synthesis_combo_logic on on fitter_effort standard fit standard fit auto_packed_registers_stratix normal normal physical_synthesis_register_duplication on on adv_netlist_opt_synth_gate_retime on on stratix_optimization_technique speed speed physical_synthesis_effort extra extra www.datasheet.in altera corporation 6?17 september 2008 design guidelines for hardcopy stratix performance improvement the results of the dse run with the seed sweep option are summarized in table 6?7 . the results in table 6?7 illustrate how the seed sweep option in dse provides additional improvement in the hardcopy stratix design, even after dse has been run on the stratix fpga project. in this example, compile point 3 using seed value = 4 turns out to be slightly beneficial over other seeds in the fitter placement. the hardcopy stratix device has an f max of 92.71 mhz. back-annotation and location assignment adjustments another technique available for improving performance in the hardcopy stratix design is manually adjusting placement and back-annotating location assignments from the placement results. these techniques should be one of the last steps taken for design optimization of hardcopy stratix devices. observing the floorplan of the 92.71 mhz compile ( figure 6?6 ), the placement of the logiclock region is stretched vertically, and additional improvement is possible if the aspect ratio of the logiclock region is defined, and placement in it is refined. table 6?7. dse results run with seed sweep compile point clock period: clk base (best) 10.868 ns 1 11.710 ns 2 11.040 ns 3 10.790 ns 4 10.945 ns 5 11.154 ns 6 11.707 ns 7 11.648 ns 8 11.476 ns 9 11.423 ns 10 11.449 ns www.datasheet.in 6?18 altera corporation september 2008 performance improvement example figure 6?6. vertically stretched logiclock region this floorplan would be better optimized if the logiclock region had a more square shape, helping the paths that go from memory-to-memory, by containing the m4k and m512 memory blocks in a smaller space, and allowing lab placement to be adjusted by the fitter. in the hardcopy stratix device, signals are routed between labs, dsp blocks, and memory blocks using the customized metal layers. the reconfigurable routing tracks in the stratix fpga device limit the routing paths and delays between elements in the hardcopy stratix device. this flexibility allows for aspect ratio changes in logiclock regions, so the raw distance between points becomes the critical factor, and not the usage of available routing resources in the fpga. for the final placement optimization in this example, the logiclock region was fixed in a square region that encompassed two columns of m4k blocks, four columns of m512 blocks, two columns of dsp blocks, and enough labs to fit the remaining resources required. after compiling the design with these new logiclock assignments, the performance increased to 93.46 mhz in the hardcopy stratix device. the critical path and logiclock region location can be seen in the zoomed-in area of the floorplan ( figure 6?7 ). yo u c a n s ee i n figure 6?7 that the critical path shown is from an m4k block to an m512 block through several levels of logic. the placement of the memory blocks can be optimized manually, since the logiclock region contains more memory blocks than necessary. www.datasheet.in altera corporation 6?19 september 2008 design guidelines for hardcopy stratix performance improvement figure 6?7. critical path and logiclock region using the critical path ?fly lines? as a guide for placement optimization, manual location assignments were made for some of the m512 and m4k instances used in the design. the resulting compile improved the f max to 94.67 mhz. the new critical path ( figure 6?8 ) shows how placement of all path elements are confined to a much smaller area. as a result, the routing distances and delays are smaller through the path. fly lines in zoomed-in portion of floorplan www.datasheet.in 6?20 altera corporation september 2008 performance improvement example figure 6?8. new critical path examining this new critical path placement, you can see that there is room for further performance improvement through additional location assignments. the current slowest path is 9.775 ns of delay. manually moving the labs in this critical path and placing them between the m4k and m512 endpoints, and subsequently recompiling, shows improved results not only for this path, but for several other paths, as this path contained a major timing bottleneck. the critical path between this start and endpoint was reduced to 8.797 ns ( figure 6?9 ). however, the entire design only improved to 100.30 mhz because other paths are now the slowest paths in the design. this illustrates that fixing one major bottleneck path can raise the entire design performance since one high fanout node can affect multiple timing paths, as was the case in this example. www.datasheet.in altera corporation 6?21 september 2008 design guidelines for hardcopy stratix performance improvement figure 6?9. improved results in summary, this design example started with 65.30 mhz in the stratix fpga device, and was improved to 74.34 mhz. it was then taken from the stratix fpga device compile and improved to 100.30 mhz in the hardcopy stratix design, for a performance improvement of 35%. conclusion using performance-optimization techniques specifically for hardcopy stratix devices can achieve significant performance improvement over the stratix fpga prototype device. many of these changes must be incorporated up-front in the hardcopy_fpga_prototype so that your design is properly prepared for performance improvement after running the hardcopy timing optimization wizard. the example discussed in this chapter demonstrates the process for performance improvement and various features in the quartus ii software available for use when optimizing your stratix fpga prototype and hardcopy stratix device. it also demonstrates the importance of planning ahead for the hardcopy stratix design implementation while continuing to work in the hardcopy_fpga_prototype design if you are going to seek performance improvement in the hardcopy stratix device. www.datasheet.in 6?22 altera corporation september 2008 document revision history document revision history table 6?8 shows the revision history for this chapter. table 6?8. document revision history date and document version changes made summary of changes september 2008 v1.4 updated chapter number and metadata. ? june 2007 v1.3 updated the ?background information? section. completed minor typographical updates. ? december 2006 v1.2 updated revision history. ? march 2006 formerly chapter 21; no content change. ? october 2005 v1.1 updated graphics minor edits ? july 2005 v1.0 initial release of chapter 21, design guidelines for hardcopy stratix performance improvement. ? www.datasheet.in |
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